H05K3/062

METHODS FOR PRODUCING AN ETCH RESIST PATTERN ON A METALLIC SURFACE
20180146556 · 2018-05-24 · ·

Methods and composition sets for forming etch-resist masks on a metallic surface are provided. The method may include applying a composition comprising a first reactive component onto a metallic surface to form a primer layer; and image-wise printing by a nonimpact printing process on the primer layer another composition comprising a second reactive component to produce an etch-resist mask, wherein when droplets of the second composition contact the primer layer, the reactive components undergo a chemical reaction so as to immobilize the droplets. The set may include a first liquid composition comprising a fixating reactive component and a second liquid composition comprising an etch-resist reactive component, wherein the fixating reactive component and the fixating reactive component are capable undergoing a chemical reaction to form a bi-component material that is insoluble in water and in an acidic etch solution.

SELECTIVE METALLIZATION OF AN INTEGRATED CIRCUIT (IC) SUBSTRATE

Embodiments of the present disclosure describe selective metallization of an integrated circuit (IC) substrate. In one embodiment, an integrated circuit (IC) substrate may include a dielectric material and metal crystals having a polyhedral shape dispersed in the dielectric material and bonded with a ligand that is to ablate when exposed to laser light such that the metal crystals having the ablated ligand are activated to provide a catalyst for selective electroless deposition of a metal. Other embodiments may be described and/or claimed

Method of manufacturing a multilayer flexible printed circuit board
09883584 · 2018-01-30 · ·

[Problem to be Solved] A multilayer flexible printed circuit board having a strip line advantageous to folding is provided. [Solution] A multilayer flexible printed circuit board 100 of an embodiment is a multilayer flexible printed circuit board having a strip line foldable at a folding part F1, the board including: a flexible insulative substrate 30; an inner layer circuit pattern 5 provided inside the flexible insulative substrate 30 and including a signal line 6 extending in a predetermined direction; a ground thin film 14a constituting a ground layer at least in the folding part F1 out of a ground layer of the strip line and constituted of a nonelectrolytic plating coat 14 formed on the flexible insulative substrate 30; and a protective layer 20 that covers the ground thin film 14a and is in close contact with an exposed part 19 from which the flexible insulative substrate 30 is exposed.

Methods and systems of forming metal interconnect layers using engineered templates
12165881 · 2024-12-10 ·

Described herein are methods and systems for forming metal interconnect layers (MILs) on engineered templates and transferring these MILs to device substrates. This off-device approach of forming MILs reduces the complexity and costs of the overall process, allows using semiconductor processes, and reduces the risk of damaging the device substrates. An engineered template is specially configured to release a MIL when the MIL is transferred to a device substrate. In some examples, the engineered template does not include barrier layers and/or adhesion layers. In some examples, the engineered template comprises a conductive portion to assist with selective electroplating. Furthermore, the same engineered template may be reused to form multiple MILs, having the same design. During the transfer, the engineered template and device substrate are stacked together and then separated while the MIL is transitioned from the engineered template to the device substrate.

Methods And Systems Of Forming Metal Interconnect Layers Using Engineered Templates
20250069900 · 2025-02-27 ·

Described herein are methods and systems for forming metal interconnect layers (MILs) on engineered templates and transferring these MILs to device substrates. This off-device approach of forming MILs reduces the complexity and costs of the overall process, allows using semiconductor processes, and reduces the risk of damaging the device substrates. An engineered template is specially configured to release a MIL when the MIL is transferred to a device substrate. In some examples, the engineered template does not include barrier layers and/or adhesion layers. In some examples, the engineered template comprises a conductive portion to assist with selective electroplating. Furthermore, the same engineered template May be reused to form multiple MILs, having the same design. During the transfer, the engineered template and device substrate are stacked together and then separated while the MIL is transitioned from the engineered template to the device substrate.

TAMPER-RESPONDENT SENSORS WITH FORMED FLEXIBLE LAYER(S)
20170091491 · 2017-03-30 ·

Tamper-respondent electronic circuit structures, electronic assembly packages, and methods of fabrication are provided which include, at least in part, a tamper-respondent sensor. The tamper-respondent sensor includes one or more formed flexible layers of, for instance, a dielectric material, having opposite first and second sides, and circuit lines defining at least one resistive network. The circuit lines are disposed on at least one of the first side or the second side of the formed flexible layer(s). The formed flexible layer(s) with the circuit lines includes curvatures, and the circuit lines overlie, at least in part, the curvatures of the formed flexible layer(s). In certain embodiments, the formed flexible layer(s) may be one or more corrugated layers or one or more flattened, folded layers.

TAMPER-RESPONDENT SENSORS WITH FORMED FLEXIBLE LAYER(S)
20170094803 · 2017-03-30 ·

Methods of fabricating tamper-respondent electronic circuit structures and electronic assembly packages are provided which include, at least in part, a tamper-respondent sensor including one or more formed flexible layers of, for instance, a dielectric material, having opposite first and second sides, and circuit lines defining at least one resistive network. The circuit lines are disposed on at least one of the first side or the second side of the formed flexible layer(s). The formed flexible layer(s) with the circuit lines includes curvatures, and the circuit lines overlie, at least in part, the curvatures of the formed flexible layer(s). In certain embodiments, the formed flexible layer(s) may be one or more corrugated layers or one or more flattened, folded layers.

Method of forming stacked wiring
09566790 · 2017-02-14 · ·

A method of forming a stacked wiring includes forming a first adhesion layer on a substrate, forming a first wiring on the first adhesion layer, etching the first adhesion layer and the first wiring by the same first wet etching so that the first wiring is in a reverse trapezoid shape in which a first width of a top surface is larger than a second width of a bottom surface contacting the first adhesion layer as a cross-section in a direction intersecting with a first wiring extending direction, covering the top surface and a side surface of the first wiring with a second adhesion layer, forming a second wiring on the second adhesion layer, and etching the second adhesion layer and the second wiring by the same second wet etching so that the second adhesion layer and the second wiring remain on only the top surface of the first wiring.

Method of producing printed circuit boards

A method of producing a printed circuit board includes providing a base substrate that is a film or plate, has first and second substrate sides and consists partly of an electrically non-conducting organic polymer material, where the first substrate side is covered with a capping metal layer, and regionally removing the capping metal layer, wherein regionally removing the capping metal layer includes applying a mask layer to the capping metal layer, regionally removing the mask layer by a laser so that the first substrate side is divided into at least one first subregion, in which the first substrate side is covered only with the capping metal layer, and into at least one second subregion, in which the first substrate side is covered with the capping metal layer and by the mask layer, and removing the capping metal layer in the at least one first subregion by an etching solution.

Method for manufacturing circuit board
12328828 · 2025-06-10 · ·

A method for manufacturing a circuit board includes providing a composite material film including a metal film and a polymeric film, disposing a dielectric layer on the polymeric film to form a stacked structure, forming a circuit layer with a contact pad on a substrate, bonding the stacked structure onto the substrate and the circuit layer, and forming a first opening extending through the metal film to form a patterned metal film. The dielectric layer directly contacts the substrate and entirely covers the circuit layer. The method further includes plasma etching the dielectric layer with the patterned metal film as a mask to form a second opening in the dielectric layer and expose the contact pad in the second opening, removing the composite material film, and depositing a conductive material in the second opening to form a conductive blind hole electrically connected to the contact pad.