A package structure includes: a substrate, where a plurality of welding pads are disposed on a surface of the substrate, each of the plurality of welding pads includes a bottom layer welding pad and a top layer welding pad which are stacked onto one another, and at least two of peripheral surfaces of the top layer welding pad are protruded relative to peripheral surfaces of the bottom layer welding pad; a chip located on the substrate and spaced apart from the substrate; and a plurality of solder balls, where the plurality of solder balls are welded to the substrate and the chip, and the plurality of solder balls wrap the top layer welding pads.

A flexible printed circuit and a manufacturing method thereof, an electronic device module and an electronic device are provided. The flexible printed circuit includes a main sub-circuit board and a bridge sub-circuit board; the main sub-circuit board includes a first substrate, and a first bridge end, a second bridge end, a first wiring portion, and a second wiring portion on the first substrate; the bridge sub-circuit board includes a second substrate, and a third bridge end, a fourth bridge end, and a third wiring portion on the second substrate, the third bridge end and the fourth bridge end are electrically connected by the third wiring portion, and the bridge sub-circuit board is configured to be mounted on the main sub-circuit board by electrically connecting the third bridge end and the fourth bridge end to the first bridge end and the second bridge end, respectively.

The joining material of the present invention is a joining material which contains a first metal powder and a second metal powder having a higher melting point than the first metal powder, in which the first metal powder is formed of Sn or an alloy containing Sn, the second metal powder is formed of a CuNi alloy in which a proportion of Ni is 5 wt % or more and 30 wt % or less, a CuNiCo alloy in which a total of a proportion of Ni and a proportion of Co is 5 wt % or more and 30 wt % or less, or a CuNiFe alloy in which a total of a proportion of Ni and a proportion of Fe is 5 wt % or more and 30 wt % or less, and a 90% volume grain size D90 of the second metal powder is 0.1 m or more.

A lead-free solder preform includes a core layer and adhesion layer coated over surfaces of the core layer, where the preform delivers the combined merits from constituent solder alloys of the core and adhesion layers to provide both high temperature performance and improved wetting in high-temperature solder applications such as die attach. The core layer may be formed of a Bi Alloy having a solidus temperature above 260 C., and the adhesion layer may be formed of Sn, a Sn alloy, a Bi alloy, In, or an In alloy having a solidus temperature below 245 C. The solder preform may be formed using techniques such as: (1) electroplating a core ribbon with an adhesion material, (2) cladding an adhesion material foil onto a core ribbon, and/or (3) dipping a core ribbon in a molten adhesion alloy bath to allow thin layers of adhesion material to adhere to a core ribbon.

A lead-free solder alloy includes 2.0% by mass or more and 4.0% by mass or less of Ag, 0.3% by mass or more and 0.7% by mass or less of Cu, 1.2% by mass or more and 2.0% by mass or less of Bi, 0.5% by mass or more and 2.1% by mass or less of In, 3.0% by mass or more and 4.0% by mass or less of Sb, 0.001% by mass or more and 0.05% by mass or less of Ni, 0.001% by mass or more and 0.01% by mass or less of Co, and the balance being Sn.

A soldering material (1) for active soldering, in particular for active soldering of a metallization (3) to a carrier layer (2) comprising ceramics, wherein the soldering material comprises copper and is substantially silver-free.

The present invention provides a solder material containing Sn or a Sn-containing alloy and 40 to 320 ppm by mass of A, the solder material including an As-enriched layer.

A method of fabricating a circuit board structure is provided. The method includes providing a core substrate; forming an insulation layer on the core substrate; forming a patterned metal layer on the insulation layer, wherein the patterned metal layer includes a wiring layer and a pad; forming a first metal pillar on the pad, wherein the first metal pillar has a top surface; and forming a first solder resist layer on the patterned metal layer and the first metal pillar, wherein the first solder resist layer has a first opening exposing the first metal pillar, and the first opening has a bottom surface, wherein the top surface of the metal pillar is higher than or equal to the bottom surface of the first opening.

A solder alloy has an alloy composition consisting of, in mass %, Ag: from 3.2 to 3.8%, Cu: from 0.6 to 0.8%, Ni: from 0.01 to 0.2%, Sb: from 2 to 5.5%, Bi: from 1.5 to 5.5%, Co: from 0.001 to 0.1%, Ge: from 0.001 to 0.1%, and optionally at least one of Mg, Ti, Cr, Mn, Fe, Ga, Zr, Nb, Pd, Pt, Au, La and Ce: 0.1% or less in total, with the balance being Sn. The alloy composition satisfies the following relationship (1): 2.93{(Ge/Sn)+(Bi/Ge)}(Bi/Sn) (1). In the relationship (1), each of Sn, Ge, and Bi represents the content (mass %) in the alloy composition.

A method includes vacuum annealing on a substrate having at least one solder bump to reduce voids at an interface of the at least one solder bump. A die is mounted over the substrate.