The invention relates to a method for producing a solder connection between a plurality of components (12A, 12B) in a process chamber (74) sealed off from its surroundings by heating and melting solder material (16) which is arranged between the components (12A, 12B) to be connected. It is proposed that the components (12A, 12B) to be connected are provisionally connected with a bonding material (18) to form a solder group (10) in which the components (12A, 12B) are fixed relative to one another in a joining position.

An apparatus and method for providing an artificial standoff to the bottom of leads on a QFN device sufficient to provide a gap that changes the fluid dynamics of solder flow and create a unique capillary effect that drives solder up the of leads of a UN device when it is attached to a printed wiring board (PWB).

A method for manufacturing a flex inlay is provided. The method includes providing a flexible printed circuit having opposed surfaces. The method includes attaching components to a surface of the flexible printed circuit. The method includes applying a coverlay over at least one surface of the flexible printed circuit, wherein the coverlay is patterned to not cover any components attached to the surface of the flexible printed circuit. The coverlay at least in part forms an essentially planar surface of the flex inlay.

A welding quality processing method and device, and a circuit board. The method includes: obtaining warpage data of each circuit board layer in a multi-layer circuit board under a preset welding temperature change curve; performing simulation according to a stacked state of the multi-layer circuit board and the warpage data to generate a warpage level of each region in the multi-layer circuit board in the stacked state; and processing the multi-layer circuit board according to the warpage level.

A method of manufacturing a printed circuit board assembly includes providing a circuit board, positioning a plurality of components including at least one thermally-sensitive component having a maximum temperature threshold on the circuit board, positioning a customized protective heat shield on the thermally-sensitive component, exposing the circuit board (having the thermally-sensitive component disposed thereon and the customized protective heat shield disposed on the thermally-sensitive component) to a high-temperature environment wherein temperatures exceed the maximum temperature threshold of the thermally-sensitive component, and removing the customized protective heat shield from the thermally-sensitive component. Customized protective heat shields are also provided.

Embodiments include a reflowable grid array (RGA) interposer, a semiconductor packaged system, and a method of forming the semiconductor packaged system. The RGA interposer includes a plurality of heater traces in a substrate. The RGA interposer also includes a plurality of vias in the substrate. The vias extend vertically from the bottom surface to the top surface of the substrate. The RGA interposer may have one of the vias between two of the heater traces, wherein the vias have a z-height that is greater than a z-height of the heater traces. The heater traces may be embedded in a layer of the substrate, where the layer of the substrate is between top ends and bottom ends of the vias. Each of the plurality of heater traces may include a via filament interconnect coupled to a power source and a ground source. The heater traces may be resistive heaters.

A flexible wiring board includes: an insulator; a wiring layer supported by the insulator; a first terminal unit including connection terminals provided at one end of the wiring layer; and a second terminal unit including connection terminals provided at the other end. A portion of the wiring layer from a part adjacent to the first terminal unit to a part adjacent to the second terminal unit is provided between first and second insulator layers included in the insulator. First and second holes formed in the first or second insulator layer are provided in an intermediate portion in a first direction from the first terminal unit to the second terminal unit and are spaced apart from each other in the first direction, and an insulator region adjacent to the first hole in a second direction is adjacent to at least a part of the second hole in the first direction.

A method and system for heat bonding a chip to a substrate by means of heat bonding material disposed there between. At least the substrate is preheated from an initial temperature to an elevated temperature below a damage temperature of the substrate. A light pulse applied to the chip momentarily increases the chip temperature to a pulsed peak temperature below a peak damage temperature of the chip. The momentarily increased pulsed peak temperature of the chip causes a flow of conducted heat from the chip to the bonding material, causing the bonding material to form a bond.

A connection structure including: a first circuit member having a plurality of first electrodes; a second circuit member having a plurality of second electrodes; and an intermediate layer having a plurality of bonding portions electrically connecting the first electrodes and the second electrodes, in which at least one of the first electrode and the second electrode that are connected by the bonding portion is a gold electrode, and 90% or more of the plurality of bonding portions include a first region containing a tin-gold alloy and connecting the first electrode and the second electrode and a second region containing bismuth and being in contact with the first region.

A solder joint, for bonding an electrode of a circuit board to an electrode of an electronic component, that includes: an Sn—Bi-based solder deposited on the electrode of the circuit board; and a solder alloy deposited on the electrode of the electronic component. The Sn—Bi-based solder alloy has a lower melting point than the solder alloy deposited on the electrode of the electronic component. Fine Bi phases in the solder joint each have an area of less than or equal to 0.5 μm.sup.2. Coarse Bi phases in the solder joint each have an area of greater than 0.5 μm.sup.2 and less than or equal to 5 μm.sup.2. A proportion of the fine Bi phases among the fine Bi phases and the coarse Bi phases is greater than or equal to 60%.