Patent classifications
H05K3/424
Method for producing a printed circuit board
A method for producing a printed circuit board is disclosed, In the method, a slot is formed in a substrate having at least three layers with the slot extending through at least two of the layers. The slot has a length and a width with the length being greater than the width. The sidewall of the substrate surrounding the slot is coated with a conductive layer. Then, the conductive layer is separated into at least two segments that are electrically isolated along the side wall of the substrate.
Method for forming circuits using seed layer and etchant composition for selective etching of seed layer
The present invention relates to a method for forming a circuit using a seed layer. The method for forming a circuit using a seed layer according to the present invention, may realize a fine pitch, increase the adhesion of the circuit, and prevent the migration phenomenon.
Silicone contact element
A contact element for use between electronic components like computer chips and printed circuit boards, or the connection between an electronic component in a test socket to provide high current, high density, and high frequency connections between the electronic components. The contact element preferably achieves a good connection between electrical components when they are connected and pressed together. The contact element is preferably made of a conductive silicone rubber which has been plated.
Method of manufacturing wafer level low melting temperature interconnections
A method of manufacturing a wafer assembly includes forming an array of planar wafer level metal posts extending from a surface of a substrate of a first wafer. After forming the array of posts, an oxide layer is applied over the surface of the first wafer and around the array of posts, the oxide layer being applied at a temperature of below 150 degrees Celsius.
WIRING CIRCUIT BOARD AND PRODUCING METHOD THEREOF
A wiring circuit board includes a base insulating layer, a conductive layer, and a metal protective film in order toward one side in a thickness direction. The conductive layer includes a signal wiring and a terminal continuous therewith. The signal wiring has one surface in the thickness direction, and first and second surfaces continuous with the one surface and disposed to face each other in a width direction. The terminal has one surface in the thickness direction, and the other surface disposed to face the one surface at the other side in the thickness direction at spaced intervals thereto. The other surface of the terminal is exposed from the base insulating layer toward the other side in the thickness direction. The metal protective film covers the one surface of the signal wiring and one surface of the terminal but not both first or second surfaces.
Leveler compositions for use in copper deposition in manufacture of microelectronics
An aqueous electrolytic composition and a process for electrodeposition of copper on a dielectric or semiconductor base structure using the aqueous electrolytic composition. The process includes (i) contacting a metalizing substrate comprising a seminal conductive layer on the base structure with an aqueous electrolytic deposition composition; and (ii) supplying electrical current to the electrolytic deposition composition to deposit copper on the substrate. The aqueous electrolytic composition comprises: (a) copper ions; (b) an acid; (c) a suppressor; and (d) a quaternized poly(epihalohydrin) comprising n repeating units corresponding to structure 1N and p repeating units corresponding to structure 1P: ##STR00001##
PRINTED WIRING BOARD
A printed wiring board includes a first conductor layer, an insulating layer formed on the first conductor layer, a second conductor layer formed on a surface of the insulating layer and including a conductor circuit, and a via conductor formed in an opening formed in the insulating layer and connecting the first and second conductor layers. The second conductor layer and via conductor include a seed layer and an electrolytic plating layer formed on the seed layer such that the seed layer has a first layer and a second layer formed on the first layer, the first layer has a width greater than a width of the second layer in cross section of the conductor circuit in the second conductor layer and that the electrolytic plating layer has a width greater than the width of the first layer in cross section of the conductor circuit in the second conductor layer.
Single step electrolytic method of filling through holes in printed circuit boards and other substrates
A method of copper electroplating in the manufacture of printed circuit boards. The method is used for filling through-holes and micro-vias with copper. The method includes the steps of: (1) preparing an electronic substrate to receive copper electroplating thereon; (2) forming at least one of one or more through-holes and/or one or more micro-vias in the electronic substrate; and (3) electroplating copper in the at one or more through-holes and/or one or more micro-vias by contacting the electronic substrate with an acid copper electroplating solution. The acid copper plating solution comprises a source of copper ions; sulfuric acid; a source of chloride ions; a brightener; a wetter; and a leveler. The acid copper electroplating solution plates the one or more through-holes and/or the one or more micro-vias until metallization is complete.
Intermediate substrate and fabrication method thereof
An intermediate substrate is provided with a plurality of conductive posts and support members arranged at opposite sides of a coreless circuit structure and insulating layers encapsulating the conductive posts and the support members. Through the arrangement of the support members and the insulating layers, the intermediate substrate can meet the rigidity requirement so as to effectively resist warping and achieve an application of fine-pitch circuits.
METHOD OF MANUFACTURING MULTI-LAYER CIRCUIT BOARD INCLUDING EXTREME FINE VIA AND MULTI-LAYER CIRCUIT BOARD MANUFACTURED BY THE SAME
A method for manufacturing a multi-layer circuit board including an extreme fine via according to an embodiment of the disclosure may include: providing a board having one surface on at least a part of which an upper conductive layer is formed and the other surface on at least a part of which a lower conductive layer is formed; forming a lower metal layer on the other surface of the board; forming a first resist layer on the one surface of the board through a photolithography process, and forming a first opening on the first resist layer; forming a metal pillar by plating the first opening by using an electrolytic plating method; removing the first resist layer; forming an insulating layer on a location from which the first resist layer is removed; and evenly polishing the metal pillar and the insulating layer.