The present invention relates to a method for forming a circuit using a seed layer. The method for forming a circuit using a seed layer according to the present invention, may realize a fine pitch, increase the adhesion of the circuit, and prevent the migration phenomenon.

The disclosed technology generally relates to forming metallization structures for integrated circuit devices by plating, and more particularly to plating metallization structures that are thicker than masking layers used to define the metallization structures. In one aspect, a method of metallizing an integrated circuit device includes plating a first metal on a substrate in a first opening formed through a first masking layer, where the first opening defines a first region of the substrate, and plating a second metal on the substrate in a second opening formed through a second masking layer, where the second opening defines a second region of the substrate. The second opening is wider than the first opening and the second region encompasses the first region of the substrate.

A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.

The present invention provides a method of fabricating an embedded circuit board, including: providing an inner laminated structure (10) which is a double-sided circuit board; providing a third circuit board (103) and a fourth circuit board (104), and respectively laminating them on two sides of the inner laminated structure (10); two spaced through holes (30) are formed in the structure obtained in the previous step; electroplating an outer surface of the third circuit board (103) and the fourth circuit board (104) and an inner surface of the through holes (30) to form a first plating layer (50); removing a structure between the two through holes (30) to form a slot (40) having the two through holes (30) at two ends; the electronic component (200) is received and fixed in a middle portion of the slot (40) such that electrodes (201) of the electronic component (200) are directed to the two ends of the slot (40) and electrically connect to the first plating layer (50); providing a first circuit board (101) and a second circuit board (102), respectively laminating them on two sides of the structure obtained in the previous step to embed the electronic component (200); performing surface treatment on the structure obtained in the previous step to obtain an embedded circuit board (100). The present invention also provides an embedded circuit board (100) fabricated by the above manufacturing method.

A ceramic circuit board and a method of making are provided. The ceramic circuit board includes a substrate and a composite material layer. The composite material layer is formed on the substrate and comprises metal oxide powders and ceramic powders. The composite material layer has an interface layer which is transformed from the metal oxide powders by reduction and includes comprises zero-valent metal, lower-valent metal oxide and eutectic mixture reduced from the metal oxide powders of the composite material layer.

Embodiments are generally directed to non-planar on-package via capacitor. An embodiment of an embedded capacitor includes a first plate that is formed in a package via; a dielectric layer that is applied on the first plate; and a second plate that is formed in a cavity in the dielectric layer, wherein the first plate and the second plate are non-planar plates.

A polymer composed of a reaction product of an amine and a quinone. The quinone is a Michael addition receptor. The polymer may be an additive for a copper electroplating bath. The polymer may function as a leveler and enable the copper electroplating bath to have high throwing power and provide copper deposits with reduced nodules.

A method of manufacturing a wafer assembly includes forming an array of planar wafer level metal posts extending from a surface of a substrate of a first wafer. After forming the array of posts, an oxide layer is applied over the surface of the first wafer and around the array of posts, the oxide layer being applied at a temperature of below 150 degrees Celsius.

An aqueous electrolytic composition and a process for electrodeposition of copper on a dielectric or semiconductor base structure using the aqueous electrolytic composition. The process includes (i) contacting a metalizing substrate comprising a seminal conductive layer on the base structure with an aqueous electrolytic deposition composition; and (ii) supplying electrical current to the electrolytic deposition composition to deposit copper on the substrate. The aqueous electrolytic composition comprises: (a) copper ions; (b) an acid; (c) a suppressor; and (d) a quaternized poly(epihalohydrin) comprising n repeating units corresponding to structure 1N and p repeating units corresponding to structure 1P:

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A wiring substrate includes a first wiring layer; a first insulation layer including a reinforcement material and a first opening extending through the reinforcement material and exposing a partial region of an upper surface of the first wiring layer, in which an end of the reinforcement material projects in the first opening; a second insulation layer not including a reinforcement material, covering an upper surface of the first insulation layer, a wall surface of the first opening, and a first part of the partial region and an entire surface of the reinforcement material projecting in the first opening, and including a second opening exposing a second part of the partial region; and a second wiring layer including a wiring portion formed on an upper surface of the second insulation layer and a via portion formed in the second opening and connecting the wiring portion to the first wiring layer.