A printed wiring board includes a core substrate, a first resin insulating layer formed on a first surface of the core substrate, a second resin insulating layer formed on a second surface of the core substrate on the opposite side of the first surface, an electronic component accommodated in opening portion formed in the core substrate, and a filling resin filling space formed between the electronic component and an inner wall of the opening portion and including resin material that is different from resin material forming the first and second resin insulating layers. The core substrate has a first conductor pattern forming a first outermost layer of the core substrate and a second conductor pattern forming a second outermost layer of the core substrate on the opposite side of the first conductor pattern, and the filling resin is filling spaces formed in the second conductor pattern of the core substrate.

A printed wiring board includes a first conductor layer forming an inner conductor layer, a second conductor layer forming a first outemiost conductor layer, a third conductor layer forming a second outermost conductor layer, insulating layers including first and second insulating layers, first via conductors connecting the first and second conductor layers, and second via conductors connecting the first and third conductor layers. The first conductor layer has thickness greater than thicknesses of the second and third conductor layers, the second conductor layer includes component mounting pads positioned to mount an electronic component on the second conductor layer and extending outside component mounting region corresponding to projection region of the component, and the first via conductors include a first set of the first via conductors formed directly underneath the component mounting region and a second set of the first via conductors formed on outer side of the component mounting region.

A printed wiring board includes a laminate including resin insulating layers and conductor layers such that the resin insulating layers and the conductor layers are laminated alternately and that the laminate has a through hole opening to a first surface of the laminate and a component accommodating cavity that accommodates an electronic component and having an opening part formed on a second surface of the laminate on the opposite side with respect to the first surface. The through hole is formed through the laminate such that the through hole is extending to the component accommodating cavity, and the laminate has a resin coating formed on an inner wall surface of the through hole.

A chip package structure including a molding compound, a carrier board, a chip, a plurality of conductive pillars and a circuit board is provided. The carrier board includes a substrate and a redistribution layer. The substrate has a first surface and a second surface. The redistribution layer is disposed on the first surface. The chip and the conductive pillars are disposed on the redistribution layer. The molding compound covers the chip, the conductive pillars, and the redistribution layer. The circuit board is connected with the carrier board, wherein the circuit board is disposed on the molding compound, such that the chip is located between the substrate and the circuit board, and the chip and the redistribution layer are electrically connected with the circuit board through the conductive pillars. Heat generated by the chip is transmitted through the substrate from the first surface to the second surface to dissipate.

A suspension board and an inspection substrate are integrally supported by a support frame. In the suspension board, first and second insulating layers are laminated on a support substrate in this order. Part of a line is formed on the first insulating layer, and the remaining line is formed on the second insulating layer. A via connecting the part of the line to the remaining line is formed in the second insulating layer. In the inspection substrate, the first and second insulating layers are laminated on the support substrate in this order. A first inspection conductor layer is formed on the first insulating layer, and a second inspection conductor layer is formed on the second insulating layer. A via connecting the first inspection conductor layer to the second inspection conductor layer is formed in the second insulating layer.

A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.

The present invention provides a process and a structure of forming conductive vias using a light guide. In an exemplary embodiment, the process includes providing a via in a base material in a direction perpendicular to a plane of the base material, applying a photoresist layer to an interior surface of the via, inserting a light guide into the via, exposing, by the light guide, a portion of the photoresist layer to light, thereby resulting in an exposed portion of the photoresist layer and an unexposed portion of the photoresist layer, removing a portion of the photoresist layer, and plating an area of the via, where the photoresist has been removed, with a metal, thereby resulting in a portion of the via plated with metal and a portion of the via not plated with metal.

A method for manufacturing traces of a printed circuit board (PCB) comprises an application of the periodic pulse reverse (PPR) pattern plating process. In the first stage, walls and bottoms in drilled holes of the PCB are modified with reduced graphene oxide (rGO) so that the vias can be formed by filling with copper and a very thin copper layer can be formed on the substrate through the electroplating process. In the second stage, a pattern of very fine traces with width/space less than 30/30 m is formed on the thin copper layer and then the traces are formed through the PPR pattern plating process. After removing unwanted copper layer, the traces with even thicknesses and square profiles are achieved and thus conform to requirements of the high density interconnection (HDI) technology.

A method of copper electroplating in the manufacture of printed circuit boards. The method is used for filling through-holes and blind micro-vias with copper. The method includes the steps of: (1) preparing an electronic substrate to. receive copper electroplating thereon: (2) forming at least one of one or more through-holes and/or one or more blind micro-vias in the electronic substrate; and (3) electroplating copper in the at one or more through-holes and/or one or more blind micro-vias by contacting the electronic substrate with an acid copper electrolyte. The acid copper electrolyte is used to plate the one or more through-holes and/or the one or more blind micro-vias using a complex waveform including pulse reverse plating. DC plating and/or synchronous pulse plating. The complex waveforms can be used for filling through-holes and blind microvias with copper without defects.

Pulse plating methods which include a forward pulse but no reverse pulse inhibit or reduce dimpling and voids during copper electroplating of through-holes in substrates such as printed circuit boards. The pulse plating methods may be used to fill through-holes with copper where the through-holes are coated with electroless copper or flash copper.