A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board (10) comprises the following steps: drilling a hole on a substrate (11), the hole comprising a blind hole and/or a through hole (S1); on a surface (12) of the substrate, forming a photoresist layer having a circuit negative image (S2); forming a conductive seed layer on the surface (12) of the substrate and a hole wall (19) of the hole (S3); removing the photoresist layer, and forming a circuit pattern on the surface (12) of the substrate (S4), wherein Step S3 comprises implanting a conductive material below the surface (12) of the substrate and below the hole wall (19) of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

A component carrier includes an electrically insulating layer structure with a first main surface and a second main surface, a through hole extends through the electrically insulating layer structure between the first main surface and the second main surface. The through hole has a first tapering portion extending from the first main surface and a second tapering portion extending from the second main surface. The through hole is delimited by a first plating structure on at least part of the sidewalls of the electrically insulating layer structure and a second plating structure formed separately from and arranged on the first plating structure. The second plating structure includes an electrically conductive bridge structure connecting the opposing sidewalls.

A composite substrate structure includes a circuit substrate, a first anisotropic conductive film, a first glass substrate, a dielectric layer, a patterned circuit layer and a conductive via. The first anisotropic conductive film is disposed on the circuit substrate. The first glass substrate is disposed on the first anisotropic conductive film and has a first surface and a second surface opposite to the first surface. The first glass substrate includes a first circuit layer, a second circuit layer and at least one first conductive via. The first circuit layer is disposed on the first surface. The second circuit layer is disposed on the second surface. The first conductive via penetrates the first glass substrate and is electrically connected to the first circuit layer and the second circuit layer. The first glass substrate and the circuit substrate are respectively located on two opposite sides of the first anisotropic conductive film.

The present invention offers a device requiring a reduced number of manufacturing processes and providing high electrical reliability, and a method for manufacturing the device. The method for manufacturing the device forms through holes in a substrate, fills the through holes with a conductive material through electroplating from a first surface side of the substrate, polishes the conductive material to form through wirings, and forms an element portion on the first surface side. Then, the method processes the substrate so that the positions of the end faces of the through wirings measured from the substrate surface on the first surface side are made smaller in depth than the positions of the end faces of the through wirings measured from the substrate surface on the second surface side.

A multilayer substrate includes a plurality of plates laminated in a thickness direction of the multilayer substrate, a resin layer provided between the plurality of plates adjacent in the thickness direction, an internal conductive layer provided between the plurality of plates adjacent in the thickness direction, and an external conductive layer provided over an outer surface of each plate of the plurality of plates located at both ends in the thickness direction, wherein a total thickness of the internal conductive layer and the external conductive layer is equal to or less than 25% of a total thickness of the plurality of plates.

A plating method of a circuit board includes first to fifth steps. The first step is implemented by providing a substrate, and the substrate has a first board surface and a second board surface opposite to the first board surface. The second step is implemented by forming a thru-hole in the substrate, and the thru-hole penetrates from the first board surface to the second board surface. The third step is implemented by detachably bonding a carrier onto the second board surface of the substrate to cover the thru-hole, and a portion of the carrier covering the thru-hole is defined as a plated region. The fourth step is implemented by plating the plated region of the carrier to form a metal post that is filled fully within the thru-hole. The fifth step is implemented by tearing off the carrier from the substrate and the metal post.

A circuit board includes a baseboard, a first conductive circuit layer, a second conductive circuit layer, at least one through hole, and a number of conductive lines. The first conductive circuit layer includes a number of first conductive circuit lines formed on a first side of the baseboard. The second conductive circuit layer includes a number of second conductive circuit lines formed on a second side of the baseboard. The through hole is defined through the first conductive circuit layer, the baseboard, and the second conductive circuit layer. The number of conductive lines are formed in an inner wall of the through hole and spaced apart around the through hole. Each conductive line electrically couples one of the first conductive circuit lines to a corresponding one of the second conductive circuit lines.

A method of manufacturing a through-hole electrode substrate includes forming a plurality of through-holes in a substrate, forming a plurality of through-hole electrodes by filling a conductive material into the plurality of through-holes, forming a first insulation layer on one surface of the substrate, forming a plurality of first openings which expose the plurality of through-hole electrodes corresponding to each of the plurality of through-hole electrodes, on the first insulation layer and correcting a position of the plurality of first openings using the relationship between a misalignment amount of a measured distance value of an open position of a leaning through-hole among the plurality of through-holes and of a design distance value of the open position of the leaning through-hole among the plurality of through-holes with respect to a center position of the substrate.

The present disclosure relates to a wiring board and a manufacturing method that simultaneously solve problems of stress and heat release A wiring board as one aspect of the present disclosure includes a glass substrate as a core member, and a plurality of through holes arranged in a cyclic manner in the glass substrate. The through holes are filled with different kinds of filling materials. A wiring board manufacturing method as one aspect of the present disclosure includes: a through hole formation step of forming through holes arranged in a cyclic manner in a glass substrate serving as a core member; and a filling step of forming a protecting sheet on the glass substrate, and filling through holes with a filling material through openings formed in the protecting sheet. The present disclosure can be applied to a wiring board that has a through-electrode-equipped glass substrate as the core member.

A semiconductor device has a first semiconductor die stacked over a second semiconductor die which is mounted to a temporary carrier. A plurality of bumps is formed over an active surface of the first semiconductor die around a perimeter of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. A plurality of conductive vias is formed through the encapsulant around the first and second semiconductor die. A portion of the encapsulant and a portion of a back surface of the first and second semiconductor die is removed. An interconnect structure is formed over the encapsulant and the back surface of the first or second semiconductor die. The interconnect structure is electrically connected to the conductive vias. The carrier is removed. A heat sink or shielding layer can be formed over the encapsulant and first semiconductor die.