A wiring body includes: a core insulating base material having a first main surface and a second main surface; a signal line and a first power supply line provided on the first main surface; a second power supply line provided on the second main surface and electrically connected to the first power supply line; a first dielectric layer laminated on the first main surface so as to embed the signal line and the first power supply line; a first ground layer provided on the first dielectric layer; a second dielectric layer laminated on the second main surface so as to embed the second power supply line; and a second ground layer provided on the second dielectric layer and sandwiching at least the signal line together with the first ground layer.

A component carrier includes an electrically insulating layer structure, a first electrically conductive layer structure, a second electrically conductive layer structure, and a laser through-hole with an electrically conductive medium filling at least part of the through-hole. The first electrically conductive layer structure covers a first side of the electrically insulating layer structure and has a first window extending through the first electrically conductive layer structure formed by etching using a conformal mask. The second electrically conductive layer structure covers an opposed side of the electrically insulating layer structure and has a second window extending through the second electrically conductive layer structure formed by etching using a conformal mask. The laser through-hole extends through the electrically insulating layer structure. At least a portion of at least one sidewall of the electrically conductive layer structures delimiting the windows is tapered.

A method for manufacturing a display substrate, a display substrate, a display panel and a display device are provided. The method includes: disposing a mask plate including an occlusion area above a base substrate, an orthographic projection of occlusion area on the base substrate partially overlapping a folding area of the base substrate; forming an inorganic layer pattern with an opening on the base substrate by using mask plate, an orthographic projection of opening on the base substrate partially overlapping the folding area of base substrate. An orthographic projection of opening on the base substrate partially overlaps the folding area of base substrate. The folding area of base substrate is occluded by mask plate. The inorganic layer is formed on the base substrate by using mask plate. Effect of conveniently and quickly removing a portion the inorganic layer located in the folding area can be achieved without removing the portion.

The printed circuit board includes, a first conductive layer including copper foil, an insulating base layer, and a second conductive layer including copper foil in this order, and includes a via-hole laminate that is stacked on an inner circumference and a bottom of a connection hole extending through the first conductive layer and the base layer in a thickness direction. The via-hole laminate has an electroless copper plating layer stacked on the connection hole and an electrolytic copper plating layer stacked on the electroless copper plating layer. The copper foil has copper crystal grains oriented in a (100) plane orientation, and an average crystal grain size of copper of 10 μm or more. The electroless copper plating layer includes palladium and tin, and an amount of the palladium stacked per unit area of a surface of the copper foil is 0.18 μg/cm.sup.2 or more and 0.40 μg/cm.sup.2 or less.

A wiring substrate includes: a base material; a first through-hole and a second through-hole that are formed in the base material; magnetic material that is filled in the first through-hole; a third through-hole that is formed in the magnetic material; a first plating film that covers an inner wall surface of the third through-hole; and a second plating film that covers an inner wall surface of the second through-hole and the first plating film. The first plating film includes a first electroless plating film that is in contact with the inner wall surface of the third through-hole, and a first electrolytic plating film that is laminated on the first electroless plating film.

The present application provides a method for manufacturing a printed circuit board and a printed circuit board. The method for manufacturing a printed circuit board includes: providing a core board, wherein the core board includes an insulating baseplate, and a first surface and/or a second surface opposite to the first surface of the insulating baseplate is provided with a plurality of pads; and laminating a medium layer on a side of the insulating baseplate provided with the plurality of pads to form a laminated layer at least partially embedded among the plurality of pads.

A method for optimized filling holes and manufacturing fine lines on a printed circuit board (PCB) carries out the two processes separately. The inner wall of the hole is metalized with reduced graphene oxide (rGO) and then electroplated to fill the hole with copper. The processes are individually performed and thus operating parameters are considered independently. As a result, the copper-plating fillings are evenly compact and the fine lines have square profiles.

A method for manufacturing a printed circuit board includes forming a through hole in an insulating layer of the printed circuit board, filling the through hole by plating to form a plating layer on the insulating layer, and removing the plating layer from the insulating layer; and forming a circuit pattern on the insulating layer.

A component carrier with a stack including an electrically insulating layer structure and an electrically insulating structure has a tapering blind hole formed in the stack and an electrically conductive plating layer extending along at least part of a horizontal surface of the stack outside of the blind hole and along at least part of a surface of the blind hole. A minimum thickness of the plating layer at a bottom of the blind hole is at least 8 μm. A demarcation surface of the plating layer in the blind hole and facing away from the stack extends laterally outwardly from the bottom of the blind hole towards a lateral indentation and extends laterally inwardly from the indentation up to an outer end of the blind hole. An electrically conductive structure fills at least part of a volume between the plating layer and an exterior of the blind hole.

A wiring substrate includes a multilayer core substrate including a core layer, core conductor layers, and core insulating layers, a first laminate formed on first surface of the substrate and including insulating layers and conductor layers such that each insulating layer includes resin without reinforcing material, and a second laminate formed on second surface of the substrate and including insulating layers and conductor layers such that each insulating layer includes resin without reinforcing material. The multilayer core substrate includes through-hole conductors penetrating through the core layer, and via conductors formed on the through-hole conductors and penetrating through the core insulating layers such that the through-hole conductors and via conductors connect outermost core conductor layers on the first and second surface sides, each of the core layer and core insulating layers includes insulating resin including reinforcing material, and the core layer has thickness greater than thickness of each core insulating layer.