To produce a wiring substrate having excellent electrical characteristics with conduction failure in a hole formed in a layer made of a fluororesin material sufficiently suppressed without conducting an etching treatment using metal sodium. A process for producing a wiring substrate, which comprises forming a hole in a laminate comprising a first conductor layer, a layer (A) which is made of a fluororesin material containing a melt-moldable fluororesin having specific functional groups and a reinforcing fiber substrate and which has a dielectric constant from 2.0 to 3.5, a second conductor layer, an adhesive layer and a layer (B) made of a cured product of a thermosetting resin laminated in this order, applying, to an inner wall surface of the hole, either one or both of a treatment with a permanganic acid solution and a plasma treatment without conducting an etching treatment using metal sodium, and then forming a plating layer.

Provided is a manufacturing method of circuit board, including a first substrate, a second substrate, a third substrate, a fourth substrate, multiple conductive structures, and a conductive via structure. The third substrate has an opening and includes a first dielectric layer. The opening penetrates the third substrate, and the first dielectric layer fills the opening. Multiple conductive structures are formed so that the first substrate, the second substrate, the third substrate, and the fourth substrate are electrically connected through the conductive structures to define a ground path. A conductive via structure is formed to penetrate the first substrate, the second substrate, the first dielectric layer of the third substrate, and the fourth substrate. The conductive via structure is electrically connected to the first substrate and the fourth substrate to define a signal path, and the ground path surrounds the signal path.

A multilayer substrate includes a lamination body including a first resin substrate, a second resin substrate, and a bonding layer that are hot-pressed. A first conductor pattern including a surface defined by a plated film is disposed on a first surface of the first resin substrate. A second conductor pattern including a surface defined by a plated film is disposed on a second surface of the first resin substrate. A third conductor pattern including a surface defined by a plated film is disposed on a third surface of the second resin substrate. A fourth conductor pattern including a surface defined by a plated film is disposed on a fourth surface of the second resin substrate. The first conductor pattern is located closer to one outermost layer than the second conductor pattern is. The second conductor pattern is thinner than the first conductor pattern.

A multi-layer circuit board is formed by positioning a top sub having traces on at least one side to one or more pairs of composite layers, each composite layer comprising an interposer layer and a sub layer. Each sub layer which is adjacent to an interposer layer having an interconnection aperture, the interconnection aperture positioned adjacent to interconnections having a plated through via or pad on each corresponding sub layer. Each interposer aperture is filled with a conductive paste, and the stack of top sub and one or more pairs of composite layers are placed into a lamination press, the enclosure evacuated, and an elevated temperature and laminated pressure is applied until the conductive paste has melted, connecting the adjacent interconnections, and the boards are laminated together into completed laminated multi-layer circuit board.

Method of constructing a printed circuit board, preferably with one lamination step: constructing multilayer cores wherein each multilayer core includes a sheet of cured dielectric material having a layer of metal on each side of the sheet of cured dielectric material; patterning each layer of metal to form wiring traces; forming a sheet of uncured dielectric material; embedding a solder element in the sheet of the uncured dielectric material; alternately stacking the multilayer cores with the sheets of uncured dielectric material, the sheet of the uncured dielectric material having the embedded solder element positioned so as to be aligned with wiring traces in adjacent layers of metal in adjacent multilayer cores; heating the solder element so as to cause the solder element to melt; and hot pressing the stack of multilayer cores and sheets of uncured dielectric material to cause curing of the sheets of uncured dielectric material.

An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.

A flexible circuit board includes two first wiring boards, a first adhesive, and a first conductive structure. Each of the two first wiring boards includes a first bent portion, and two first bent portions of the two wiring boards is connected to each other. The first adhesive layer is sandwiched between the two first bent portions. The first conductive structure penetrates the two first bent portions and the first adhesive layer and electrically connects the two first bent portions.

A testing substrate includes a first build-up structure and a ceramic substrate. The ceramic substrate is arranged on the first build-up structure. The first bonding interface between the first build-up structure and the ceramic substrate includes a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface. A manufacturing method of a testing substrate and a probe card are also provided.

A magnetic PCB generated by simultaneously spin-spraying a ferrite ion solution and an oxidant solution on a substrate plate while the substrate plate is rotated at a speed 40 rpm to about 300 rpm and heated at 40? C. to 300? C.

An interconnect topology that includes vertical trench routing in a substrate is disclosed. In one embodiment, the interconnect comprises a substrate having a plurality of layers including a first ground plane layer; a pair of signal conductors that form a differential signal pair, each conductor of the pair of signal conductors having a first portion and a second portion, the second portion extending from the first portion into at least one of the plurality of layers, wherein width of the second portion is less than width of the first portion; and wherein the first ground plane layer is only a first partial layer and has a first void region that is closer to the pair of signal conductors than the first partial layer.