A method for filling a via on a printed circuit board formulates a paste as a dispersion of copper particulate that includes nanocopper particles in a solvent and a binder and depositing the paste into a via cavity formed in the printed circuit board. Heating the paste-filled cavity removes most of the solvent. The method sinters the deposited paste in the via cavity, planarizes the sintered via, and overplates the filled via with copper.

A wiring substrate includes a first build-up part including an insulating layer and a conductor layer, and a second build-up part laminated on the first build-up part and including an insulating layer and a conductor layer. The minimum width and minimum inter-wiring distance of wirings in the first build-up part are smaller than the minimum width and minimum inter-wiring distance of wirings in the second build-up part. The insulating layer in the first build-up part includes resin and inorganic particles including first inorganic particles partially embedded in the resin and second inorganic particles completely embedded in the resin such that the first inorganic particles have first portions protruding from the resin and second portions embedded in the resin, respectively. The insulating layer of the first build-up part has a surface covered by the conductor layer and including a surface of the resin and exposed surfaces of the first portions.

This conductive paste is such that the printing properties and sintering properties are superior and is formed such that resistance of wiring after sintering is lowered. This conductive paste is characterized by being formed from copper-based metal particles and by an aspect ratio (dmax/dmin), which is defined as the ratio of the maximum diameter (dmax) and minimum diameter (dmin) for the metal particles, being greater than or equal to 1.0 and smaller than 2.2.

A printed wiring board includes a first conductor layer including a first conductor circuit and a second conductor circuit formed adjacent to the first circuit, a resin insulating layer formed on the first conductor layer such that the insulating layer is filling space between the first and second conductor circuits, and a second conductor layer formed on the insulating layer such that distance (T) between the first and second conductor layers is in the range of 4.5 m to 10.5 m. The resin insulating layer includes inorganic particles having average particle diameter (D1) such that ratio (D1/S) of the diameter (D1) to distance (S) of the space is less than 0.25 and that ratio (D1/T) of the diameter (D1) to the distance (T) is less than 0.25, where the distance (S) of the space between the first and second conductor circuits is in the range of 4.5 m to 10.5.

A polymer composition that comprises an aromatic polyester, a laser activatable additive, and a mineral filler is provided. The mineral filler has a median size of about 35 micrometers or less and the laser activatable additive has a mean size of about 1000 nanometers or less.

A wiring board includes: an inorganic insulating layer having a via hole formed so as to penetrate the inorganic insulating layer in a thickness direction thereof; a conductive layer disposed on the inorganic insulating layer; and a via conductor which adheres to an inner wall of the via hole and is connected with the conductive layer. The inorganic insulating layer includes a first section including a plurality of inorganic insulating particles partly connected to each other, and a resin portion located in gaps between the inorganic insulating particles, and a second section which is interposed between the first section and the via conductor, including a plurality of inorganic insulating particles partly connected to each other, and a conducting portion composed of part of the via conductor which is located in gaps between the inorganic insulating particles.

A printed wiring board includes a first insulating layer, a connection conductor layer including wiring, a second insulating layer covering the connection conductor layer, a conductor layer including first and second electrodes such that the first electrode mounts a first electronic component and the second electrode mounts a second electronic component, and via conductors including first and second via conductors. The first via conductor connects the first electrode and wiring. The second via conductor connects the second electrode and wiring. The conductor layer includes a seed layer and an electrolytic plating layer. The seed layer includes a first layer formed on the first insulating layer and a second layer formed on the first layer, a width of the first layer is larger than a width of the second layer, and a width of the electrolytic plating layer is larger than the width of the first layer of the seed layer.

An electronic device including an electronic unit and a redistribution layer is disclosed. The electronic unit has connection pads. The redistribution layer is electrically connected to the electronic unit and includes a first insulating layer, a first metal layer and a second insulating layer. The first insulating layer is disposed on the electronic unit and has first openings disposed corresponding to the connection pads. The first metal layer is disposed on the first insulating layer and electrically connected to the electronic unit through the connection pads. The second insulating layer is disposed on the first metal layer. The first insulating layer includes first filler particles, and the second insulating layer includes second filler particles. The first filler particles have a first maximum particle size, the second filler particles have a second maximum particle size, and the second maximum particle size is greater than the first maximum particle size.

A wiring board according to the present disclosure includes a first insulation layer in which first insulating fillers are dispersed, and a second insulation layer located on an upper surface of the first insulation layer. The first insulation layer includes a protruding filler located protruding from the upper surface of the first insulation layer among the first insulating fillers and a coating film covering a part or all of a protruding surface of the protruding filler. The coating film has a structure in which a tin layer and a silane coupling agent layer are layered in this order. The second insulation layer covers the upper surface of the first insulation layer including the coating film.

A method for manufacturing a dielectric sheet, includes the steps of extrusion molding a mixture including powder polytetrafluoroethylene and spherical silica at a temperature lower than or equal to a melting point of the polytetrafluoroethylene, and calendering a sheet body obtained by the extrusion molding. A mass ratio of the silica with respect to the polytetrafluoroethylene is 1.3 or greater. An average particle diameter of the silica is 0.1 m or greater but 3.0 m or less. A reduction ratio of the extrusion molding is 8 or less.