H05K2201/0269

CIRCUIT BOARD
20200315004 · 2020-10-01 ·

A circuit board according to an embodiment of the present invention comprises: a first metal layer; an insulating layer disposed on the first metal layer and comprising boron nitride agglomerate particles coated with a resin; and a second metal layer disposed on the insulating layer, wherein: one of both surfaces of the first metal layer, on which the insulating layer is disposed, is in at least partial contact with one surface of the insulating layer; one of both surfaces of the second metal layer, on which the insulating layer is disposed, is in at least partial contact with the other surface of the insulating layer; a plurality of grooves are formed on a surface which is one of both surfaces of at least one of the first metal layer and the second metal layer and which has the insulating layer disposed thereon; at least some of the particles are arranged in at least some of the plurality of grooves; the width (W) of at least one of the plurality of grooves is 1 to 1.8 times D50 of the particles; and a ratio (D/W) of the depth (D) to the width (W) of at least one of the plurality of grooves is 0.2 to 0.3.

DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF
20200194906 · 2020-06-18 ·

A display device includes a display panel. A flexible printed circuit board is electrically connected to the display panel. A first pad is disposed on the display panel. A second pad is disposed on the flexible printed circuit board and overlaps the first pad. A first anisotropic conductive film is disposed between the first pad and the second pad. The first anisotropic conductive film is configured to bond the first pad to the second pad. The first anisotropic conductive film includes a conductive polymer. The first anisotropic conductive film includes at least one first conductive region that electrically connects the first pad and the second pad and at least one first insulating region.

Multilayer ceramic substrate

A multilayer ceramic substrate according to the present invention includes a plurality of base layers that are laminated containing a low-temperature co-fired ceramic material, a plurality of first constraint layers which contain a metal oxide not completely sintered at the sintering temperature of the low-temperature co-fired ceramic material and which are located between the base layers, and a protective layer which contains the metal oxide and which is in contact with an outermost base layer of the plurality of base layers in the lamination direction, and wherein X1>X2, where X1 is a content of the metal oxide in a surface section of the protective layer and X2 is a content of the metal oxide in a boundary section of the protective layer that is in contact with the outermost base layer.

MULTILAYER CERAMIC SUBSTRATE

A multilayer ceramic substrate according to the present invention includes a plurality of base layers that are laminated containing a low-temperature co-fired ceramic material, a plurality of first constraint layers which contain a metal oxide not completely sintered at the sintering temperature of the low-temperature co-fired ceramic material and which are located between the base layers, and a protective layer which contains the metal oxide and which is in contact with an outermost base layer of the plurality of base layers in the lamination direction, and wherein X1>X2, where X1 is a content of the metal oxide in a surface section of the protective layer and X2 is a content of the metal oxide in a boundary section of the protective layer that is in contact with the outermost base layer.

WIRING BOARD
20200035575 · 2020-01-30 · ·

A wiring board of the present disclosure includes: a first insulating layer including a surface; a second insulating layer including un upper surface and a lower surface and locating above the surface of the first insulating layer; a wiring conductor layer formed on the surface of the first insulating layer, includes a via land; and a via hole conductor penetrating from the upper surface to the lower surface of the second insulating layer. The via hole conductor includes a via bottom being in contact with the via land. Crystal grains in the via bottom are smaller than crystal grains in the via land.

CONNECTION STRUCTURE
20200008304 · 2020-01-02 · ·

A connection structure: a first electronic component having a terminal pattern in which a plurality of terminals are arranged side by side in a radial form and a second electronic component having a terminal pattern corresponding to the terminal pattern of the first electronic component are anisotropically conductively connected using an anisotropic conductive film, (i) the effective connection area per terminal is 3000 m.sup.2 or more, and the number density of conductive particles in the anisotropic conductive film is 2000 particles/mm.sup.2 or more and 20000 particles/mm.sup.2 or less, (ii) as the anisotropic conductive film, adopted is an anisotropic conductive film in which the conductive particles are arranged in a lattice form, and the arrangement pitch and the arrangement direction are configured such that each terminal captures three or more conductive particles, or (iii) as the anisotropic conductive film, adopted is an anisotropic conductive film having a multiple circular region.

RESIN COMPOSITION FOR SEMICONDUCTOR PACKAGE AND RESIN COATED COPPER COMPRISING SAME

A resin composition for a semiconductor package according to an embodiment includes a resin composition that is a composite of a resin and a filler disposed in the resin, wherein the filler includes at least one concave portion provided on a surface, wherein a content of the filler has a range of 10 vol. % to 40 vol % of a total volume of the resin composition, and wherein a porosity corresponds to a volume occupied by the concave portion in a total volume of the filler and has a range of 20% to 35%.

Substrate for high-frequency printed wiring board

A first embodiment of a substrate for a high-frequency printed wiring board according to the present disclosure is directed to a substrate for a high-frequency printed wiring board, the substrate including: a dielectric layer including a fluororesin and an inorganic filler; and a copper foil layered on at least one surface of the dielectric layer, wherein a surface of the copper foil at the dielectric layer side has a maximum height roughness (Rz) of less than or equal to 2 m, and a ratio of the number of inorganic atoms of the inorganic filler to the number of fluorine atoms of the fluororesin in a superficial region of the dielectric layer at the copper foil side is less than or equal to 0.08.

Multilayer ceramic substrate

A multilayer ceramic substrate according to the present invention includes a plurality of base layers that are laminated containing a low-temperature co-fired ceramic material, a plurality of first constraint layers which contain a metal oxide not completely sintered at the sintering temperature of the low-temperature co-fired ceramic material and which are located between the base layers, and a protective layer which contains the metal oxide and which is in contact with an outermost base layer of the plurality of base layers in the lamination direction, and wherein X1>X2, where X1 is a content of the metal oxide in a surface section of the protective layer and X2 is a content of the metal oxide in a boundary section of the protective layer that is in contact with the outermost base layer.

Substrate for high-frequency printed wiring board

A first embodiment of a substrate for a high-frequency printed wiring board according to the present disclosure is directed to a substrate for a high-frequency printed wiring board, the substrate including: a dielectric layer including a fluororesin and an inorganic filler; and a copper foil layered on at least one surface of the dielectric layer, wherein a surface of the copper foil at the dielectric layer side has a maximum height roughness (Rz) of less than or equal to 2 ?m, and a ratio of the number of inorganic atoms of the inorganic filler to the number of fluorine atoms of the fluororesin in a superficial region of the dielectric layer at the copper foil side is less than or equal to 0.08.