A circuit board includes at least two circuit board units stacked together. Each circuit board unit includes a substrate and a circuit layer. The substrate defines a conductive hole penetrating therethrough. The conductive hole provided with a conductor therein. One side of the substrate further defines a groove, the groove including a concave portion aligned with the conductive hole. The circuit layer includes a connection pad located in the concave portion. The connection pad is shaped as a conductive protrusion, which surrounds and is electrically connected to the conductor. The circuit layer is located in the groove, and the conductive hole is electrically connecting the circuit layers of the circuit board units.

A printed wiring board according to an aspect of the present invention includes a base film having insulation properties and a conductive pattern including multiple wiring portions laminated, the conductive pattern running on at least one surface of the base film, wherein each wiring portion includes a first conductive portion and a second conductive portion coating an outer surface of the first conductive portion, wherein an average width of each wiring portion is 10 μm or greater to 50 μm or smaller, and an average thickness of the second conductive portion is 1 μn or greater to smaller than 8.5 μm.

Provided is a wiring circuit board that includes a first insulating layer, a conductive pattern disposed on the first insulating layer, and a second protective layer disposed between the first insulating layer and protecting the conductive pattern. The second protective layer consists of a metal oxide.

A method for forming a printed circuit board includes: forming on a substrate a first conductive layer for a first edge connector pin and a first conductive layer for a second edge connector pin, wherein the first conductive layer for the first edge connector pin and the first conductive layer for the second edge connector pin are electrically coupled to one another via a first conductive layer for an electrical bridging element; electroplating a second conductive layer onto both the first conductive layer for the first edge connector pin and the first conductive layer for the second edge connector pin via a plating current conductor; and removing at least a portion of the electrical bridging element to electrically separate the first edge connector pin from the second edge connector pin.

A wiring board includes an insulating base including a first principal surface, a second principal surface opposite to the first principal surface, and a first through hole penetrating the insulating base from the first principal surface to the second principal surface, a functional material provided inside the first through hole, a first insulating layer covering the first principal surface, and a first surface of the functional material, and a second insulating layer covering the second principal surface, and a second surface of functional material. A second through hole is formed in the first insulating layer, the functional material, and the second insulating layer, and a conductive layer is formed on a wall surface of the second through hole.

A ceramic electronic component that includes an electronic component body having a superficial base ceramic layer; a surface electrode on a surface of the electronic component body; and a covering ceramic layer covering a peripheral section of the surface electrode. The peripheral section of the surface electrode that is covered by the covering ceramic layer has a thin portion located on a central side of the surface electrode and which is thinner than a central section of the surface electrode, and a width of the thin portion is 20% or more of a width of the peripheral section of the surface electrode that is covered by the covering ceramic layer.

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a core with a first surface and a second surface, where the core comprises glass. In an embodiment, a first buildup layer is over the first surface of the core, and a second buildup layer is under the second surface of the core. In an embodiment, the electronic package further comprises a via through the core between the first surface of the core and the second surface of the core, and a plane into the first surface of the core, where a width of the plane is greater than a width of the via.

A substrate for a printed circuit board according to an embodiment of the present invention includes a base film having an insulating property, and a conductive layer formed on at least one of surfaces of the base film. In the substrate for a printed circuit board, at least the conductive layer contains titanium in a dispersed manner. The conductive layer preferably contains copper or a copper alloy as a main component. A mass ratio of titanium in the conductive layer is preferably 10 ppm or more and 1,000 ppm or less. The conductive layer is preferably formed by application and heating of a conductive ink containing metal particles. The conductive ink preferably contains titanium or a titanium ion. The metal particles are preferably obtained by a titanium redox process including reducing metal ions using trivalent titanium ions as a reducing agent in an aqueous solution by an action of the reducing agent.

A method of plating a copper substrate with gold that reduces or eliminates the presence of microvoids at the interface of the gold/copper substrate is described. Suitably, live entry of the substrate into the plating bath is performed with application of external current to the bath such that no portion of the substrate is exposed to the bath for more than one second without the application of the external current. Increase of the applied current for gold strike to the mass-transfer-limit for gold reduction accomplishes the full measure of improvement in eliminating microvoids.

A circuit board according to an embodiment includes an insulating layer; and a lead pattern portion disposed on the insulating layer, wherein the lead pattern portion includes: a first portion disposed on the insulating layer; and a second portion extending from one end of the first portion; wherein the first portion is disposed overlapping the insulating layer in a vertical direction, wherein the second portion is disposed in an outer region of the insulating layer and does not overlap the insulating layer; and wherein the lead pattern portion has a centerline average roughness in a range of 0.05 .Math.m to 0.5 .Math.m or a 10-point average roughness in a range of 1.0 .Math.m to 5.0 .Math.m.