Patent classifications
H05K2201/0347
CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF
The disclosure provides a method for manufacturing a circuit board, which includes: (1) providing a substrate, forming a through hole in the substrate; (2) filling the through hole with a conductor to form a conductive hole; (3) providing a peelable film to cover the substrate; (4) forming a groove by laser, the groove including a concave portion; (5) performing a surface treatment on a wall of the groove; (6) removing the peelable film; (7) forming a seed layer; (8) making a circuit layer to obtain a circuit board unit, the circuit layer including a connection pad, the connection pad shaped as a conductive protrusion which surrounds and is electrically connected to the conductor; (9) repeating step (1) to step (8) at least once; and (10) laminating the circuit board units. The disclosure also provides a circuit board.
PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD
A printed wiring board includes resin insulating layers including an outermost resin insulating layer, conductor layers laminated on the resin insulating layers, a copper layer formed in the outermost insulating layer, and metal bumps formed on the copper layer such that the bumps have upper surfaces protruding from the outermost insulating layer and that each metal bump includes Ni film, Pd film and Au film. The copper layer is reduced in diameter toward upper surface side such that the copper layer has upper and bottom surfaces and each upper surface has diameter that is smaller than diameter of each bottom surface, the outermost insulating layer has cylindrical sidewalls formed such that at least part of the copper layer is not in contact with the sidewalls, and the bumps are formed such that the Ni film is filling spaces between the copper layer and the sidewalls of the outermost insulating layer.
WIRING BOARD AND METHOD OF MANUFACTURING THE SAME
A wiring board includes a first wiring layer formed on one surface of a core layer, a first insulating layer formed on the one surface of the core layer so as to cover the first wiring layer, a via wiring embedded in the first insulating layer, a second wiring layer formed on a first surface of the first insulating layer, and a second insulating layer thinner than the first insulating layer formed on the first surface of the first insulating layer so as to cover the second wiring layer. The first wiring layer comprises a pad and a plane layer provided around the pad. One end surface of the via wiring is exposed from the first surface of the first insulating layer and directly bonded to the second wiring layer. The other end surface of the via wiring is directly bonded to the pad in the first insulating layer.
MODULE AND METHOD OF MANUFACTURING THE SAME
A module includes a ceramic multilayer substrate including a main surface; a surface-layer conductor pattern arranged on the main surface and integrally formed to include a land portion and an interconnection portion extending from the land portion; a first layer arranged to cover the land portion while exposing at least a part of the interconnection portion, the first layer having conductivity, the first layer being composed of a material that is lower in affinity to solder than a material for the surface-layer conductor pattern, and a component mounted on the first layer with solder being interposed. The solder is not in direct contact with the surface-layer conductor pattern.
PRINTED CIRCUIT SURFACE FINISH, METHOD OF USE, AND ASSEMBLIES MADE THEREFROM
A surface finish for a printed circuit board (PCB) and semiconductor wafer includes a nickel disposed over an aluminum or copper conductive metal surface. A barrier layer including all or fractions of a nitrogen-containing molecule is deposited on the surface of the nickel layer to make a barrier layer/electroless nickel (BLEN) surface finish. The barrier layer allows solder to be reflowed over the surface finish. Optionally, gold (e.g., immersion gold) may be coated over the barrier layer to create a nickel/barrier layer/gold (NBG) surface treatment. Presence of the barrier layer causes the surface treatment to be smoother than a conventional electroless nickel/immersion gold (ENIG) surface finish. Presence of the barrier layer causes a subsequently applied solder joint to be stronger and less subject to brittle failure than conventional ENIG.
PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a printed circuit board includes providing an insulating layer, forming a plating seed layer on the insulating layer, forming a first circuit pattern on the plating seed layer and a second circuit pattern on the first circuit pattern, and forming a top metal layer on the second circuit pattern. The second circuit pattern can be thinner than the first circuit pattern, and the top metal layer can be wider than the second circuit pattern.
Method of forming a solderable solder deposit on a contact pad
A method of forming a solderable solder deposit on a contact pad, comprising the steps of providing an organic, non-conductive substrate which exposes said contact pad under an opening of a first non-conductive resist layer, depositing a conductive layer inside and outside the opening such that an activated surface results, thereby forming an activated opening, electrolytically depositing nickel or nickel alloy into the activated opening such that nickel/nickel alloy is deposited onto the activated surface, electrolytically depositing tin or tin alloy onto the nickel/nickel alloy, with the proviso that the electrolytic deposition of later steps results in an entirely filled activated opening, wherein the entirely filled activated opening is completely filled with said nickel/nickel alloy, or in the entirely filled activated opening the total volume of nickel/nickel alloy is higher than the total volume of tin and tin alloy, based on the total volume of the entirely filled activated opening.
Method for manufacturing a conductor structural element and conductor structural element
A conductor structural element includes an electronic component which is inserted into a dielectric layer and connected to a conductor pattern structure consisting of an electrically conductive material applied to an electrically conductive base layer by electroplating, wherein at least one contacting element of the electronic component is inserted into an assigned mounting area, which is formed as a recess in the conductor track structure, the at least one contacting element and the conductor track structure being connected to each other in an electrically conductive manner.
Wiring board and method of manufacturing the same
A wiring board includes a first wiring layer formed on one surface of a core layer, a first insulating layer formed on the one surface of the core layer so as to cover the first wiring layer, a via wiring embedded in the first insulating layer, a second wiring layer formed on a first surface of the first insulating layer, and a second insulating layer thinner than the first insulating layer formed on the first surface of the first insulating layer so as to cover the second wiring layer. The first wiring layer comprises a pad and a plane layer provided around the pad. One end surface of the via wiring is exposed from the first surface of the first insulating layer and directly bonded to the second wiring layer. The other end surface of the via wiring is directly bonded to the pad in the first insulating layer.
BASE MATERIAL FOR PRINTED CIRCUIT BOARD AND PRINTED CIRCUIT BOARD
The base material for printed circuit board according to one aspect of the present disclosure is a base material for printed circuit board comprising a base film having an insulating property, a sintering layer inducing a plurality of copper particles and formed on at least one surface of the base film and an electroless copper plating layer formed on a surface of the sintering layer, the surface being on an opposite side to the base film, and filled in the sintering layer, and wherein a lightness L* of a surface of the electroless copper plating layer, the surface being on an opposite side to the sintering layer, is 45.0 or more and 85.0 or less, a chromaticity a* thereof is 5.0 or more and 25.0 or less, and a chromaticity b* thereof is 5.0 or more and 25.0 or less.