A printed circuit board includes a coreless substrate including an insulating body and a plurality of core wiring layers disposed on or within the insulating body, a build-up insulating layer covering at least a portion of each of an upper surface and a lower surface of the coreless substrate, and a build-up wiring layer disposed on at least one of an upper surface and a lower surface of the build-up insulating layer. A through-opening penetrates through the insulating body and is configured to receive an electronic component therein, and the first build-up insulating layer extends into the through-opening to embed the electronic component.

An antenna system includes a first printed circuit board having an array of printed circuit board antenna elements, a second circuit board having a signal distribution network for the antenna elements, and at least one first interconnect structure coupled between a bottom surface of the first printed circuit board and a top surface of the second circuit board. The first interconnect structure can include first vias having an aspect ratio of greater than 10 to 1. The vias electrically connect to respective first contacts on the bottom surface of the first circuit board and to respective second contacts on the top surface of the second circuit board.

A component carrier with a first stack and a second stack. The first stack includes at least one first electrically insulating layer structure and at least one first electrically conductive layer structure having a first connection body with a first exposed planar electrically conductive surface. The second stack includes at least one second electrically insulating layer structure and at least one second electrically conductive layer structure having a second connection body with a second exposed planar electrically conductive surface. The first stack and the second stack are connected with each other so that the first exposed planar electrically conductive surface and the second exposed planar electrically conductive surface are connected to establish a vertical two-dimensional electrically conductive connection.

An interconnection includes a circuit board assembly and a hybrid cable assembly. The circuit board assembly includes first and second outer layer assemblies and an intermediate layer assembly. The first and second outer layer assemblies each include an electrically conductive layer. A cable-receiving space is formed at a first side edge of the circuit board assembly. The hybrid cable assembly includes a dielectric waveguide system having a core and a cladding and being configured to transmit a radar wave in a frequency range from about 70 to about 300 GHz. A first conductor system configured to transmit power and/or data is disposed adjacent to the dielectric waveguide system and includes an electrically conductive inner conductor assembly inserted into the cable-receiving space and galvanically connected to a first inner-conductor connection region. The core of the dielectric waveguide system is inserted into the cable-receiving space and disposed at a waveguide connection region.

The present invention includes a method of making a RF impedance matching device in a photo definable glass ceramic substrate. A ground plane may be used to adjacent to or below the RF Transmission Line in order to prevent parasitic electronic signals, RF signals, differential voltage build up and floating grounds from disrupting and degrading the performance of isolated electronic devices by the fabrication of electrical isolation and ground plane structures on a photo-definable glass substrate.

An object of the present invention is to provide a composition for sintering capable of suppressing a crack from occurring in a wiring after sintering. Provided is the composition for sintering including silver nanoparticles, an organic dispersant for coating the silver nanoparticles, and a solvent. When the composition for sintering is heated, a weight loss rate in a range of 260 C. to 600 C. is 2.92% or less.

A method of manufacturing a component carrier. The method includes forming a stack having at least one electrically insulating layer structure and/or at least one electrically conductive layer structure, and embedding a filament in the stack.

A method for producing a waveguide in a multilayer substrate involves producing at least one cutout corresponding to a lateral course of the waveguide in a surface of a first layer arrangement comprising one or a plurality of layers. A metallization is produced on surfaces of the cutout. A second layer arrangement comprising one or a plurality of layers is applied on the first layer arrangement. The second layer arrangement comprises, on a surface thereof, a metallization which, after the second layer arrangement has been applied on the first layer arrangement, is arranged above the cutout and together with the metallization on the surfaces of the cutout forms the waveguide.

A circuit board having multiple degrees of freedom, comprises a flat board and a conductive and flexible unit disposed on the flat board. The conductive and flexible unit comprises: an inner support plate, an outer support plate, and at least one flexible connector; a hollow portion is provided on the outer support plate; the inner support plate and the flexible connector are disposed in the hollow portion; the inner and the outer support plates are connected by the flexible connector; the flexible connector comprises an outer connecting portion, an inner connecting portion corresponding to the outer connecting portion, and an extension located between the outer connecting portion and the inner connecting portion. The circuit board has a simple and compact structure; the production efficiency is high; costs are low; a multi-axis flexible anti-shaking effect can be achieved without folding a flexible structure; the resilience performance is good.

An evacuated core circuit board (10) for dissipating heat from a heat generating electronic component, the evacuated core circuit board comprising: at least one circuit layer (12) to which the heat generating electronic component (14) is electronically coupled; a base layer (16) a comprising a body structure (19) having a substantially hollow interior (20); and a dielectric layer (18) provided between at least a portion of the circuit layer (12) and the base layer (16), wherein the hollow interior (20) is at least partially evacuated.