A component carrier includes a stack having an electrically conductive layer structure, with at least one recess, on an electrically insulating layer structure; a dielectric filling medium filling at least part of the at least one recess; and a further electrically insulating layer structure on the electrically conductive layer structure and on the dielectric filling medium. A method of manufacturing a component carrier includes forming a stack having an electrically conductive layer structure, with at least one recess, on an electrically insulating layer structure; at least partially filling the at least one recess by a dielectric filling medium; and thereafter forming a further electrically insulating layer structure on the electrically conductive layer structure and on the dielectric filling medium.

A manufacturing method of a double layer circuit board comprises forming a connecting pillar on a first circuit, wherein the connecting pillar comprises a first end, connected to the first circuit, and a second end, opposite to the first end; forming a substrate on the first circuit and the connecting pillar; drilling the substrate to expose a portion of the second end of the connecting pillar, wherein the other portion of the second end of the connecting pillar is covered by the substrate; and forming a second circuit on the substrate and the portion of the second end of the connecting pillar, wherein an area of the first end connected to the first circuit layer is greater than an area of the portion of the second end connected to the second circuit layer.

Provided are an electronic component manufacturing method by which even a platable layer made of a difficult-to-plate material can be easily plated with good adhesion without using a special chemical solution or a photolithography technique, and an electronic component which has a peel strength of 0.1 N/mm or greater as measured by a copper foil peel test. A picosecond laser beam having a pulse duration on the order of a picosecond or a femtosecond laser beam having a pulse duration on the order of a femtosecond is emitted at a surface of a platable layer (2) in order to roughen the surface, a wiring pattern is formed using a mask (13), and a plated part (12) is formed on the surface of the wiring pattern.

An electronic circuit assembly comprises a circuit substrate including a top surface, a bottom surface, and a cavity formed at an edge of the circuit substrate that exposes an intermediate surface between the top surface and the bottom surface of the circuit substrate; and a laser diode including a top surface, a bottom surface, and a side surface; wherein the bottom surface of the laser diode is arranged on the intermediate surface of the circuit substrate.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface, wherein the substrate layer includes a photo-imageable dielectric (PID) and an electroless catalyst; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the first thickness is greater than the second thickness.

A method for manufacturing a touch panel includes the steps of: forming a first imprint layer; forming a first wire forming groove portion; forming a first wire; forming a spacer layer so that the spacer layer is placed over a surface of the first imprint layer in which the first wire forming groove portion has been formed and overlaps a part of the first wire; forming a second imprint layer so that the spacer layer is sandwiched between the first imprint layer and the second imprint layer; forming a second wire forming groove portion; forming a second wire; and delaminating the spacer layer from the first imprint layer and removing, together with the delaminated portion, a portion of the second imprint layer that overlaps the delaminated portion.

A method for manufacturing a circuit board includes forming a patterned first dielectric layer on a substrate; forming a first adhesive layer on the patterned first dielectric layer; forming a second dielectric layer on the first adhesive layer; patterning the second dielectric layer to expose a portion of a top surface of the first adhesive layer opposite to the substrate; and filling at least the patterned second dielectric layer with a conductive material, such that the conductive material is in contact with the top surface of the first adhesive layer.

A multi-layer circuit board is formed multiple layers of a catalytic layer, each catalytic layer having an exclusion depth below a surface, where the cataltic particles are of sufficient density to provide electroless deposition in channels formed in the surface. A first catalytic layer has channels formed which are plated with electroless copper. Each subsequent catalytic layer is bonded or laminated to an underlying catalytic layer, a channel is formed which extends through the catalytic layer to an underlying electroless copper trace, and electroless copper is deposited into the channel to electrically connect with the underlying electroless copper trace. In this manner, traces may be formed which have a thickness greater than the thickness of a single catalytic layer.

According to one embodiment, the present invention relates to a printed circuit board, comprising: a first insulating layer; an inner layer circuit pattern disposed on an upper surface of the first insulating layer; a second insulating layer, disposed on the first insulating layer, for covering the inner layer circuit pattern; a first outer layer circuit pattern integrated into a lower surface of the first insulating layer; and a second outer layer circuit pattern embedded in an upper surface of the second insulating layer, the first insulating layer comprising a thermosetting resin, and the second insulating layer comprising a photocurable resin.

The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.