A wiring substrate includes a resin insulating layer, and a conductor layer formed on the resin insulating layer and including a seed layer and a metal film formed on the seed layer such that the conductor layer has wiring patterns including wirings. The conductor layer is formed such that each of the wirings in the wiring patterns has undercut parts on side surfaces extending to the resin insulating layer, and the wirings in the conductor layer include outer wirings formed such that each of the outer wirings has the undercut part on the side surface facing an adjacent one of the wirings is smaller than the undercut part on the side surface farther from the adjacent one of the wirings.

A method of forming a high-conductivity electrical interconnect on a substrate may include forming a graphene film with a plurality of graphene members, depositing a metal over the graphene film, and providing a metallic overlay that connects the plurality of graphene members together through the depositing operation to form a covered graphene film.

A stretchable mounting board that includes a stretchable substrate having a main surface, a stretchable wiring disposed on the main surface of the stretchable substrate, a mounting electrode section electrically connected to the stretchable wiring, solder electrically connected to the mounting electrode section and including bismuth and tin, and an electronic component electrically connected to the mounting electrode section with the solder interposed therebetween. The mounting electrode section has a first electrode layer on a side thereof facing the stretchable wiring and which includes bismuth and tin, and a second electrode layer on a side thereof facing the solder and which includes bismuth and tin. A concentration of the bismuth in the first electrode layer is lower than a concentration of the bismuth in the second electrode layer, and the concentration of the bismuth in the second electrode layer is constant along a thickness direction thereof.

The present invention uses a photolithography process and an electroplating process to perform. TAV copper filling and patterning of the fabrication of the double side copper-plated layers to plate the double side copper-plated layers in advance at the TAV through holes to serve as a stress buffer layer of the aluminum nitride substrates. Then the subsequent pattern designs of the copper-plated layers are customized. According to the simulation theory calculations, it is proved that the stress which accumulates on the short-side of the copper-plated layer of the aluminum nitride substrate with the asymmetric structure may be effectively reduced to facilitate the improvement of the reliability of the aluminum nitride substrate.

A printed wiring board includes a base insulating layer, a conductor layer formed on the base layer and including first and second pads, a solder resist layer formed on the base layer such that the solder resist layer has first opening exposing the first pad and second opening exposing the second pad with diameter smaller than diameter of the first opening, and bumps including a first bump on the first pad and a second bump on the second pad such that the second bump has diameter smaller than diameter of the first bump. The first bump has a base plating layer formed in the first opening and having raised portion, and a top plating layer formed on the base plating layer, and the second bump has a base plating layer formed in the second opening and having raised portion, and a top plating layer formed on the base plating layer.

Forming aluminum circuit layers forming an aluminum circuit layers on one surface of a ceramic substrate and forming copper circuit layers are included. The copper circuit layers are formed by laminating copper boards for the circuit layers on the respective aluminum circuit layers, arranging the laminate between a pair of support boards having a convex curved surface at least on one surface so as to face to each other, moving the support boards in a facing direction to press the laminate in a lamination direction, and heating in this pressing state so that the copper boards for the circuit layers are bonded on the aluminum circuit layers respectively by solid phase diffusion. In the step of forming the copper circuit layers, the support boards are arranged so that either one of the convex curved surface is in contact with the adjacent copper boards for the circuit layers in the laminate.

A multilayer board includes a flexible substrate including insulating layers stacked and a pair of through-holes penetrating the insulating layers, and an interlayer connecting conductor in an opposing region in which the pair of through-holes opposes each other in a plan view of the insulating layers viewed from a stacking direction. A cross section of the flexible substrate taken in a lateral direction passing through the pair of through-holes and the interlayer connecting conductor and the stacking direction has a U or S shape. In the cross section, a curvature radius of an inner region located between the pair of through-holes is larger than a curvature radius of an outer region adjacent to the pair of through-holes on an outer side thereof.

An insulated circuit board having a ceramic substrate, a circuit layer on which a circuit pattern is formed and that is bonded to one surface of the ceramic substrate, and a metal layer bonded to the other surface of the ceramic substrate. The circuit layer has a first circuit layer that is bonded to the ceramic substrate and is made of aluminum and a second circuit layer that is bonded to the upper surface of the first circuit layer and is made of copper, the metal layer has a first metal layer that is bonded to the ceramic substrate and is made of aluminum and a second metal layer that is bonded to the upper surface of the first metal layer and is made of copper, and the thicknesses of the first circuit layer and the first metal layer are each 0.2 mm or more and 0.9 mm or less.

A component carrier includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, at least one first electrically conductive track extending from a vertical level defined by one of the layer structures up to a first height, at least one second electrically conductive track extending from the vertical level defined by the one of the layer structures up to a second height being larger than the first height, and at least one further electrically insulating layer structure in which the at least one first electrically conductive track and the at least one second electrically conductive track are embedded.

A component carrier includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, at least one first electrically conductive track extending from a vertical level defined by one of the layer structures up to a first height, at least one second electrically conductive track extending from the vertical level defined by the one of the layer structures up to a second height being larger than the first height, and at least one further electrically insulating layer structure in which the at least one first electrically conductive track and the at least one second electrically conductive track are embedded.