Patent classifications
H05K2201/0391
Methods and apparatus for conductive element deposition and formation
A conductive element such as an antenna, for use in electronic devices, including mobile devices such as cellular phones, smartphones, personal digital assistants (PDAs), laptops, and wireless tablets, and methods of, and apparatus for, forming the same. In one exemplary aspect, the present disclosure relates to a conductive antenna formed using deposition of conductive fluids as well as the method and equipment for forming the same. In one embodiment, a complex (3D) conductive trace is formed using two or more different print technologies via creation of different domains within the conductive trace pattern.
Electronic device including wiring on a stretchable/contractible base
An electronic device including a stretchable/contractible base and a wiring formed on the base, the wiring being divided into a first region having a shape extending in a proceeding direction and a second region in which the proceeding direction is curved. The wiring includes a first conductive layer and a second conductive layer formed of a material that makes the second conductive layer easier to be curved than the first conductive layer. The first conductive layer is formed in the first region and the second conductive layer is formed in the second region.
CIRCUIT BOARD
A circuit board according to an embodiment includes an insulating layer; and a lead pattern portion disposed on the insulating layer, wherein the lead pattern portion includes: a first portion disposed on the insulating layer; and a second portion extending from one end of the first portion; wherein the first portion is disposed overlapping the insulating layer in a vertical direction, wherein the second portion is disposed in an outer region of the insulating layer and does not overlap the insulating layer; and wherein the lead pattern portion has a centerline average roughness in a range of 0.05 .Math.m to 0.5 .Math.m or a 10-point average roughness in a range of 1.0 .Math.m to 5.0 .Math.m.
Chip part having passive elements on a common substrate
A chip part includes a substrate, a first electrode and a second electrode which are formed apart from each other on the substrate and a circuit network which is formed between the first electrode and the second electrode. The circuit network includes a first passive element including a first conductive member embedded in a first trench formed in the substrate and a second passive element including a second conductive member formed on the substrate outside the first trench.
Transparent conductive coatings for optoelectronic and electronic devices
The invention provides processes for the manufacture of conductive transparent films and electronic or optoelectronic devices comprising same.
Method for manufacturing wiring board, and wiring board
Provided is a method for manufacturing a wiring board that forms a wiring layer having favorable adhesion without a resin resist pattern. A method prepares a substrate with seed-layer including: a underlayer on the surface of an insulating substrate; and a seed layer on the surface of the underlayer, the seed layer having a predetermined pattern and containing metal; presses a solid electrolyte membrane against the seed layer and the underlayer, and applies voltage between an anode and the underlayer to reduce metal ions in the membrane and form a metal layer on the surface of the seed layer; and removes an exposed region without the seed layer and the metal layer of the underlayer to form a wiring layer including the underlayer, the seed layer and the metal layer on the surface of the substrate.
CERAMIC BOARD WITH MEMORY FORMED IN THE CERAMIC
The present disclosure is directed to a ceramic substrate that includes a plurality of contact pads, a plurality of electrical traces, and a microelectromechanical die. Contacts on the die are coupled to the plurality of contact pads through the plurality of electrical traces. The substrate also includes a plurality of memory bits formed directly on the substrate. Each memory bit is coupled between a first one of the contact pads and a second one of the contact pads.
METHOD FOR MANUFACTURING WIRING BOARD
A method for manufacturing a wiring board in which the adhesion between an underlayer and a seed layer is improved. A diffusion layer in which an element forming the underlayer and an element forming a coating layer are mutually diffused is formed between the underlayer and a wiring portion of the coating layer by irradiating the wiring portion with a laser beam. A seed layer is formed by removing a portion excluding the wiring portion of the coating layer from the underlayer. A metal layer is formed by disposing a solid electrolyte membrane between an anode and the seed layer and applying voltage between the anode and the underlayer. An exposed portion without the seed layer of the underlayer is removed from an insulating substrate.
Wiring board, flexible display panel and display device
The present disclosure discloses a wiring board used to connect a driving chip and a display panel, a flexible display panel and a display device. Signal output ends on the driving chip and signal input ends on the display panel may be arranged in pairs; and the wiring board may include fanout lines each of which is configured to connect a pair of signal output end and the signal input end. The wiring board may include a substrate; a plurality of segments of first connection lines having first resistivity is arranged on a first surface of the substrate; a plurality of segments of second connection lines having second resistivity is arranged on a second surface of the substrate opposite to the first surface. At least parts of the fanout lines are formed by connecting the first connection lines and the second connection lines.
Printed wiring board
A printed wiring board includes an insulation layer, conductive pads formed on the insulation layer and positioned to connect an electronic component, and a conductive wiring pattern including first and second conductive patterns and formed on the insulation layer such that the conductive wiring pattern is extending between the conductive pads. The first pattern includes first wiring lines, the second pattern includes second wiring lines, the first and second conductive patterns are formed such that the first wiring lines and the second wiring lines are alternately arrayed on the insulation layer, each of the first wiring lines includes a first metal layer formed on an interface with the insulation layer, each of the second wiring lines includes a second metal layer formed on an interface with the insulation layer, and the first metal layer includes a metal material which is different from a metal material forming the second metal layer.