Pastes are disclosed that are configured to coat a passage of a substrate. When the paste is sintered, the paste becomes electrically conductive so as to transmit electrical signals from a first end of the passage to ta second end of the passage that is opposite the first end of the passage. The metallized paste contains a lead-free glass frit, and has a coefficient of thermal expansion sufficiently matched to the substrate so as to avoid cracking of the sintered paste, the substrate, or both, during sintering.

A micro power distribution box is provided which includes a device, a connector/housing and a cover. The device has a substrate, at least one first finger, at least one second finger, and at least one electrical component. The at least one first finger and the at least one second finger are electrically connected to one another. The at least one first finger has first, second and third portions. The at least one second finger has first and second portions. The substrate is overmolded to the first portions of the at least one first and second fingers. The substrate is not overmolded to the second portions of the at least one first and second fingers or to the third portion of the at least one first finger. The second portions of the at least one first and second fingers extend outwardly from the substrate. The second portion of the at least one first finger is a high current contact. The second portion of the at least one second finger is a contact pin. The third portion of the at least one first finger is exposed via an aperture provided through the substrate. The at least one electrical component is directly mounted to the third portion of the at least one first finger in order to electrically connect the at least one electrical component to the at least one first finger. The connector/housing is configured to house the device therein and is configured to be connected to a mating connector. The cover is configured to be secured to the connector/housing in a manner which prevents the device from being removed from the connector/housing.

Described are various configurations of high-speed via structures. Various embodiments can reduce or entirely eliminate insertion loss in high-speed signal processing environments by using impedance compensation structures that decrease a mismatch in components of a circuit. An impedance compensation structure can include a metallic structure placed near a via to lower an impedance difference between the via and a conductive pathway connected to the via.

This disclosure describes systems, methods, and apparatus for multilayer superconducting structures comprising electroplated Rhenium, where the Rhenium operates in a superconducting regime at or above 4.2 K, or above 1.8 K where specific temperatures and times of annealing have occurred. The structure can include at least a first conductive layer applied to a substrate, where the Rhenium layer is electroplated to the first layer. A third layer formed from the same or a different conductor as the first layer can be formed atop the Rhenium layer.

A trace structure includes a substrate, at least one metal trace, and a cover. The metal trace is disposed on the substrate, and has sidewalls and a top surface. The cover is disposed on the sidewalls and the top surface of the metal trace, and the cover includes metal nanowires. The cover and the metal trace have different etch resistances.

A printed wiring board includes a base insulating layer, a conductor layer including first and second pads, a solder resist layer covering the conductor layer and having first opening exposing the first pad and second opening exposing the second pad, a first bump including base plating layer in the first opening and top plating layer on the first base layer, and a second bump including base plating layer in the second opening and top plating layer on the base layer. The second opening has smaller diameter than the first opening, and the second bump has smaller diameter than the first bump. The first base layer has flat upper surface or first recess having depth of 20 μm or less in upper central portion. The second base layer has flat upper surface, raised portion in upper central portion, or second recess shallower than the first recess in the upper central portion.

A wiring structure that includes first wiring parts which are formed of conductive wires and second wiring parts which are formed of thicker conductive wires than the conductive wires of the first wiring parts and are connected to the first wiring parts is formed by offset printing which includes the following processes. First printing process: First conductive ink for forming the first wiring parts is transferred from a first blanket to a base. Second printing process: Second conductive ink for forming the second wiring parts is transferred from a second blanket, which is different from the first blanket, to the base.

A wiring structure that includes first wiring parts which are formed of conductive wires and second wiring parts which are formed of thicker conductive wires than the conductive wires of the first wiring parts and are connected to the first wiring parts is formed by offset printing which includes the following processes. First printing process: First conductive ink for forming the first wiring parts is transferred from a first blanket to a base. Second printing process: Second conductive ink for forming the second wiring parts is transferred from a second blanket, which is different from the first blanket, to the base.

A wiring substrate includes a substrate including conductor layers and core insulating layers, and a laminate including insulating layers and conductor layers such that the conductor layers include first layer including first line pattern. The laminate includes first strip line including the first pattern, a pair of interlayer insulating layers sandwiching the first pattern, and a pair of conductor layers sandwiching the interlayer layers, the conductor layers in the substrate include second layer including second line pattern such that the substrate includes second strip line including the second pattern, a pair of core insulating layers sandwiching the second pattern, and a pair of conductor layers sandwiching the core insulating layers, and the pair of core insulating layers is thicker than the pair of interlayer layers, the second pattern is thicker than the first pattern, and line width of the second pattern is larger than line width of the first pattern.

A method is disclosed for applying an electrical conductor to an electrically insulating substrate, which comprises providing a flexible membrane with a pattern of groove formed on a first surface thereof, and loading the grooves with a composition comprising conductive particles. The composition is, or may be made, electrically conductive. Once the membrane is loaded, the grooved first surface of the membrane is brought into contact with a front or/and back of the substrate. A pressure is then applied between the substrate and the membrane(s) so that the composition loaded to the grooves adheres to the substrate. The membrane(s) and the substrate are separated and the composition in the groove is left on the surface of the electrically insulating substrate. The electrically conductive particles in the composition are then sintered to form a pattern of electrical conductors on the substrate, the pattern corresponding to the pattern formed in the membrane(s).