An example sensor interposer employing castellated through-vias formed in a PCB includes a planar substrate defining a plurality of castellated through-vias; a first electrical contact formed on the planar substrate and electrically coupled to a first castellated through-via; a second electrical contact formed on the planar substrate and electrically coupled to a second castellated through-via, the second castellated through-via electrically isolated from the first castellated through-via; and a guard trace formed on the planar substrate, the guard trace having a first portion formed on a first surface of the planar substrate and electrically coupling a third castellated through-via to a fourth castellated through-via, the guard trace having a second portion formed on a second surface of the planar substrate and electrically coupling the third castellated through-via to the fourth castellated through-via, the guard trace formed between the first and second electrical contacts to provide electrical isolation between the first and second electrical contacts.

Examples are disclosed related to forming solder joints between printed circuits by using radiant heat. One example provides a method of manufacturing an electronic device, the method comprising aligning a contact of a first printed circuit with a via of a second printed circuit. The method further comprises applying radiant heat via an infrared light source to a second surface of the second printed circuit, the radiant heat incident on the via to cause the via to conduct heat to solder located at an interface of the contact and the via, and after heating the solder to reflow, cooling the solder, thereby forming a solder joint between the contact of the first printed circuit and the via of the second printed circuit.

An example sensor interposer employing castellated through-vias formed in a PCB includes a planar substrate defining a plurality of castellated through-vias; a first electrical contact formed on the planar substrate and electrically coupled to a first castellated through-via; a second electrical contact formed on the planar substrate and electrically coupled to a second castellated through-via, the second castellated through-via electrically isolated from the first castellated through-via; and a guard trace formed on the planar substrate, the guard trace having a first portion formed on a first surface of the planar substrate and electrically coupling a third castellated through-via to a fourth castellated through-via, the guard trace having a second portion formed on a second surface of the planar substrate and electrically coupling the third castellated through-via to the fourth castellated through-via, the guard trace formed between the first and second electrical contacts to provide electrical isolation between the first and second electrical contacts.

A printed wiring board includes a first insulating layer, a conductor layer, and a second insulating layer. The conductor layer includes first and second circuits such that space is formed between the circuits, the first circuit has first and second side walls, the second circuit has third and fourth side walls such that the second wall faces the third wall, the first circuit has first, second and third portions, the second circuit has fourth, fifth and sixth portions such that the first and fourth portions, the second and fifth portions and the third and sixth portions face each other, the first circuit is formed such that the second wall of the second portion is recessed from the second wall of the first and third portions, and the first insulating layer has recess between the second and fifth portions such that the second insulating layer is filling the space and recess.

A method of producing at least one connection carrier includes: A) providing a carrier plate with a planar top face; B) applying at least one electrically insulating insulation strip to the top face and cohesively connecting the carrier plate and the insulation strip; and C) applying at least one electrically conductive conductor strip to an adhesive surface of the insulation strip and cohesively connecting the insulation strip and the conductor strip, wherein the conductor strip and the carrier plate are electrically insulated from one another by the insulation strip.

An example sensor interposer employing castellated through-vias formed in a PCB includes a planar substrate defining a plurality of castellated through-vias; a first electrical contact formed on the planar substrate and electrically coupled to a first castellated through-via; a second electrical contact formed on the planar substrate and electrically coupled to a second castellated through-via, the second castellated through-via electrically isolated from the first castellated through-via; and a guard trace formed on the planar substrate, the guard trace having a first portion formed on a first surface of the planar substrate and electrically coupling a third castellated through-via to a fourth castellated through-via, the guard trace having a second portion formed on a second surface of the planar substrate and electrically coupling the third castellated through-via to the fourth castellated through-via, the guard trace formed between the first and second electrical contacts to provide electrical isolation between the first and second electrical contacts.

A circuit board includes an insulating portion and a pattern portion on the insulating portion. The insulating portion includes a first insulating region and a second insulating region outside the first insulating region and spaced apart from the first insulating region with a separation region therebetween. The pattern portion includes a first pattern portion for signal transmission and a second pattern portion including a dummy pattern separated from the first pattern portion. The first pattern portion includes a first terminal portion on the first insulating region, a second terminal portion on the second insulating region, and a connection portion on the separation region and connecting between the first terminal portion and the second terminal portion. The second pattern portion includes a second-first pattern portion on the first insulating region and a second-second pattern portion on the second insulating region and separated from the second-first pattern portion.

A flexible cable may include a base member including a terminal portion, a conductor layer including a plurality of conductive lines disposed on the base member, and a protection layer disposed on the base member to cover at least prat of the conductor layer and to expose a portion of each of the plurality of conductive lines at the terminal portion. A length of each of the plurality of conductive lines may be longer than a length of the base member. A vibration device may include a vibration structure including a vibration layer, a first electrode layer disposed on a first surface of the vibration layer, and a second electrode layer disposed on a second surface of the vibration layer and a flexible cable electrically connected to the first electrode layer and to the second electrode layer of the vibration structure.

Embodiments include an interconnectable circuit board array. The interconnectable circuit board array includes a plurality of interconnectable circuit boards coupled together with a plurality of board to board connectors. The board to board connectors include a first lateral side conductor and a second lateral side conductor to provide electrical communication between the connect circuit boards. The board to board connectors are configured such that when two adjacent circuit boards are bent in a lateral plane with respect to one another to form an angle, one of the lateral side conductors is contracted, one of the lateral side conductors is expanded, or one of the lateral side conductors is contracted and the other lateral side conductor is expanded. Other embodiments are also included herein.

A circuit board comprises a row of solder pads adapted to be soldered to a row of contacts of a connector, a plurality of first conductive vias, and a plurality of second conductive vias. The contacts include a plurality of ground contacts and a plurality of signal contacts. The solder pads include a plurality of ground solder pads each soldered to a solder foot of one of the ground contacts and a plurality of signal solder pads each soldered to a solder foot of one of the signal contacts. The first conductive vias correspond to and are electrically connected to the ground solder pads and are electrically connected to each other by a first connection bar. The second conductive vias correspond to and are electrically connected to the ground solder pads and are electrically connected to each other by a second connection bar. The solder foot of each of the ground contacts is disposed between one of the first conductive vias and one of the second conductive vias.