A flip chip interconnection including a circuit board is disclosed. The circuit board includes a substrate, inner leads, a T-shaped circuit line and a dummy pattern. The inner leads, the T-shaped circuit line and the dummy pattern are located on an inner bonding area of the substrate. The T-shaped circuit line includes a main segment, a branch segment and a connection segment that is connected to the main segment and the branch segment. The main segment and the branch segment are extended along a lateral direction and a longitudinal direction, respectively. The dummy pattern is located between the connection segment and the inner leads.

A circuit board disclosed in the present invention includes a substrate and a circuit layer. The circuit layer is formed on a surface of the substrate and includes at least one test circuit line. The test circuit line includes a main segment and a branch segment connected with each other. The branch segment is provided to be contacted with a test equipment for electrical test so as to protect the main segment from breaking during electrical test.

A method of running a printed circuit board (PCB) trace on a PCB. The PCB comprising a plurality of PCB layers. The method comprising forming a conductive trace on at least one of the plurality of PCB layers; coupling a first portion of the conductive trace to a capacitor formed on at least one of the plurality of PCB layers; coupling a second portion, different from the first portion, of the conductive trace to a conductive material formed within a first via extending through two or more of the plurality of PCB layers; and configurably setting a length of a conductive path of the conductive trace according to a predetermined impedance. The capacitor is separated laterally in a plan view at a first distance from the first via. The length of the conductive trace in the plan view is greater than the first distance. The conductive path of the conductive trace of the length has the predetermined impedance.

A display device includes a display panel, and an electrostatic capacitive type touch panel which is formed in an overlapping manner with the display panel. A plurality of X electrodes and a plurality of Y electrodes intersecting with the X electrodes. A first signal line supplies signals to the X electrodes, a second signal line supplies signals to the Y electrodes, and the first signal line and the second signal line are formed on a flexible printed circuit board. A dummy electrode is formed adjacent to an electrode portion of each X electrode and electrode portion of each Y electrode, the dummy electrode does not overlap the X electrode and the Y electrode, and the dummy electrode does not electrically connect with the first and second signal lines.

In one embodiment, a system includes a ground layer, a first layer, a second layer, and a plurality of vias. The first layer includes a first insulating material and a plurality of first metallic strips. The second layer includes a second insulating material and a plurality of second metallic strips. The plurality of vias electrically connect one or more of the plurality of first metallic strips of the first layer to one or more of the plurality of second metallic strips of the second layer. The plurality of first metallic strips of the first layer and the plurality of second metallic strips of the second layer form a plurality of capacitors and a plurality of conductors. Each capacitor is located in the first layer. Each conductor is partially located in the first layer and partially located in the second layer.

A high-speed serial computer expansion bus circuit topology, comprises: a first signal path connecting between a first interface and a second interface, a second signal path connecting between the first interface and a third interface, a third signal path connecting between the third interface and a fourth interface, a first selector circuit having a first passive element and a second passive element which are respectively disposed in the first signal path and the second signal path, a second selector circuit having a third passive element and a fourth passive element which are respectively disposed in the second signal path and the third signal path. The second signal path is conducted when the first passive element and the second passive element are conducted, the third signal path is conducted when the third passive element and the fourth passive element are conducted.

A printed circuit board may include a controller socket, first and second sockets provided on a top surface, third and fourth sockets provided on a bottom surface, and first, second, and third branching points. The first branching point may be spaced apart from the controller socket by a first distance in a horizontal direction parallel to the top surface and may be electrically connected to the controller socket. The second branching point may be spaced apart from the first branching point by a second distance longer than the first distance and may be electrically connected to the first branching point, the first and third sockets. The third branching point may be spaced apart from the first branching point by a third distance longer than the first distance and may be electrically connected to the first branching point, the second and fourth sockets.

A circuit board electrically connected to a chip includes a substrate and a circuit layer. A first conductive line of the circuit layer includes a main line and a branch lead connected with each other. The branch lead provided to increase lead quantity for bonding with the chip includes an extension part and a bonding part which is used for bonding a bump of the chip. During thermal compression, gaps existing between the extension part and the main line and between the bonding part and the main line can prevent solder on the main line from flowing toward the bump and overflowing from the branch lead.

A communication module may include a communication ground layer. The communication module may also include a circuit board. The circuit board may be located proximate the communication ground layer. The circuit board may include a stitch layer. The stitch layer may be electrically coupled to the communication ground layer via a plurality of stitch layer vias. Additionally, the communication module may include multiple ground vias. The ground vias may be electrically coupled to a portion of the circuit board and to the communication ground layer.

A method of running a printed circuit board (PCB) trace on a PCB. The PCB comprising a plurality of PCB layers. The method comprising forming a conductive trace on at least one of the plurality of PCB layers; coupling a first portion of the conductive trace to a capacitor formed on at least one of the plurality of PCB layers; coupling a second portion, different from the first portion, of the conductive trace to a conductive material formed within a first via extending through two or more of the plurality of PCB layers; and configurably setting a length of a conductive path of the conductive trace according to a predetermined impedance. The capacitor is separated laterally in a plan view at a first distance from the first via. The length of the conductive trace in the plan view is greater than the first distance. The conductive path of the conductive trace of the length has the predetermined impedance.