Patent classifications
H05K2201/093
Durable memory device
Disclosed is a durable memory device comprising: a multilayer PCB having a plurality of circuit layers and a plurality of circuit layers insulating layers alternately arranged with each other, ach circuit layer being provided with a via through which the plurality of circuit layers are electrically connected, and the circuit layers has at least one ground layer; a memory member; a connection interface for connecting to a corresponding connecting portion of a computing device; and an anti-sulfuration-and-anti-high-voltage passive component which is disposed at the multilayer PCB and electrically connected to the connection interface and the memory member. By combining the anti-sulfuration-and-anti-high-voltage passive component and multilayer PCB, the durable memory device of the present invention is durable for the outdoor use.
DURABLE MEMORY DEVICE
Disclosed is a durable memory device comprising: a multilayer PCB having a plurality of circuit layers and a plurality of circuit layers insulating layers alternately arranged with each other, ach circuit layer being provided with a via through which the plurality of circuit layers are electrically connected, and the circuit layers has at least one ground layer; a memory member; a connection interface for connecting to a corresponding connecting portion of a computing device; and an anti-sulfuration-and-anti-high-voltage passive component which is disposed at the multilayer PCB and electrically connected to the connection interface and the memory member. By combining the anti-sulfuration-and-anti-high-voltage passive component and multilayer PCB, the durable memory device of the present invention is durable for the outdoor use.
REFERENCE METAL LAYER FOR SETTING THE IMPEDANCE OF METAL CONTACTS OF A CONNECTOR
A circuit board has an electrical circuit and a connector that is attached to the circuit board. The connector has metal contacts. A housing of the connector has an embedded reference metal layer that is disposed under a single-ended metal contact or differential metal contacts. The reference metal layer sets the impedance of the single-ended metal contact or the differential metal contacts.
Axial field rotary energy device with PCB stator panel having thermally conductive layer
An axial field rotary energy device has a PCB stator panel assembly between rotors with an axis of rotation. Each rotor has a magnet. The PCB stator panel assembly includes PCB panels. Each PCB panel can have layers, and each layer can have conductive coils. The PCB stator panel assembly can have a thermally conductive layer that extends from an inner diameter portion to an outer diameter portion thereof.
Current redistribution in a printed circuit board
In one implementation, a multilayered printed circuit board is configured to redirect current distribution. The current may be distributed by steering, blocking, or otherwise manipulating current flows. The multilayered printed circuit board includes at least one power plane layer. The power plane layer does not distribute current evenly. Instead, the power plane layer includes multiple patterns with different resistances. The patterns may include a hatching pattern, a grid pattern, a directional pattern, a slot, a void, or a continuous pattern. The pattern is a predetermined spatial variation such that current flows in a first area differently than current flows in a second area.
Anti-Interference Circuit Board and Terminal
An anti-interference circuit board and a terminal are provided. The circuit board specifically includes a substrate (10). The substrate (10) has a first surface, and a first region (14) for placing a magnetometer (2) is disposed on the first surface. A plurality of circuit layers (11, 12, 15) are disposed in the substrate (10), and the plurality of circuit layers (11, 12, 15) are disposed in a stacked manner. For example, at least a first functional circuit (20) that is configured to generate a magnetic field in a first direction and a second functional circuit (30) that is configured to generate a magnetic field in a second direction are disposed in a stacked manner and are disposed in the substrate (10). When positions of the first functional circuit (20) and the second functional circuit (30) are specifically disposed, the following is met: the first region (14) is located in vertical projections of the first functional circuit (20) and the second functional circuit (30) on the first surface. It can be learned from the foregoing descriptions that the first functional circuit (20) and the second functional circuit (30) are disposed to compensate for interference to the magnetometer (2) in the first region (14), and during disposing, the first functional circuit (20) and the second functional circuit (30) are located below the magnetometer (2), to reduce an occupied surface area of the anti-interference circuit board.
Selective ground flood around reduced land pad on package base layer to enable high speed land grid array (LGA) socket
Embodiments include a transmission line-land grid array (TL-LGA) socket assembly, a TL-LGA socket, and a package substrate. The TL-LGA socket assembly includes a TL-LGA socket having an interconnect in a housing body, the interconnect includes a vertical portion and a horizontal portion. The housing body has a top surface and a bottom surface, where the top surface is a conductive layer. The TL-LGA socket assembly also includes a package substrate having a base layer having a signal pad and a ground strip. The base layer is above the conductive layer of the housing body of the TL-LGA socket. The ground strip is above the horizontal portion of the interconnect and adjacent to the signal pad. The horizontal portion is coupled to the signal pad on the base layer. The package substrate may have a pad with a reduced pad area.
ELECTRONIC SUBSTRATE
An electronic substrate connects to a semiconductor component via a plurality of front surface terminals disposed in an array on a front surface and connects to a main substrate via a plurality of back surface terminals disposed in an array on a back surface. The electronic substrate includes: a first wiring that electrically connects the front surface terminals and the back surface terminals in the electronic substrate and is supplied with power supply from the main substrate via the back surface terminals; and a second wiring that electrically connects the front surface terminals and the back surface terminals in the electronic substrate, is supplied with power supply having the same potential as the first wiring from the main substrate via the back surface terminals, and is not electrically connected to the first wiring in the electronic substrate.
System of providing power
A system of providing power including: a preceding-stage power supply module, a post-stage power supply module and a load, connected in sequence; a projection on the mainboard of a smallest envelope area formed by contour lines of the preceding-stage power supply module and the load at least partially overlaps with a projection of the post-stage power supply module; the preceding-stage power supply module includes a plurality of sets of preceding-stage output pins and preceding-stage ground pins alternately arranged to form a first rectangular envelope area, and the load is disposed on a side of a long side of the first rectangular envelope area; and the load comprises a load input pin and a load ground pin forming a second rectangular envelope area, and a center line of the first rectangular envelope area and the second rectangular envelope area is perpendicular to the long side of the first rectangular envelope area.
Pattern-edged metal-plane resonance-suppression
Apparatuses and methods are provided for mitigating radio frequency interference and electromagnetic compatibility issues caused by the resonance of metal planes of a circuit board. A method for controlling impedance at an edge of a circuit board includes creating a cut at an edge of a plane of the circuit board. The cut extends from the edge of the plane to a point at a depth into the plane. The method can further include creating a cut pattern in the edge of the plane by repeating the cut along the edge of the plane such that an impedance of the plane at the depth is different, or lower, than an impedance of the plane at the edge of the plane. Other aspects are described.