An electronic device includes a printed circuit board (PCB). The PCB includes first and second grids disposed at a top surface and a bottom surface of the PCB, respectively. Each grid includes a plurality of footprint pins, and a plurality of vias extending through the PCB to the top and bottom surfaces. Each footprint pin includes a connecting end and a free end that opposes the connecting end. Each via includes a contact end located at one of grids and is in electrical contact with the connecting end of one of the footprint pins, and each via further includes a non-contact end that is located at the other of the grids and is not in electrical contact with any of the footprint pins. First and second connectors are mounted to the PCB top and bottom surfaces and connect with the footprint pins of the first and second grids.

A land for a surface mounted component according to an embodiment includes a land (10) for a surface mounted component includes a plurality of land regions (11a, 11b) respectively having different width. Land regions included in the plurality of land regions are combined with one another with centers in a width direction aligned in order conforming to the widths and are jointed into one land. A cutout shape (12) is provided in a center in the width direction on a side opposed to an adjacent or overlapping side of a land region having a larger width of adjacent or partially overlapping two land regions in the plurality of land regions joined into the one land.

An electronic device, including an array substrate, a pad portion disposed on the array substrate, and an integrated circuit disposed on the pad portion and comprising a bump portion. The pad portion includes a first sub-pad unit including a first pad having an inclined shape and a second sub-pad unit including a second pad having an inclined shape. The first pad and the second pad are symmetrically arranged with respect to an imaginary line that divides the pad portion. The pad portion is electrically connected with the bump portion.

Described are various configurations of high-speed via structures. Various embodiments can reduce or entirely eliminate insertion loss in high-speed signal processing environments by using impedance compensation structures that decrease a mismatch in components of a circuit. An impedance compensation structure can include a metallic structure placed near a via to lower an impedance difference between the via and a conductive pathway connected to the via.

A printed wiring board includes a base insulating layer, a conductor layer including first and second pads, a solder resist layer covering the conductor layer and having first opening exposing the first pad and second opening exposing the second pad, a first bump including base plating layer in the first opening and top plating layer on the first base layer, and a second bump including base plating layer in the second opening and top plating layer on the base layer. The second opening has smaller diameter than the first opening, and the second bump has smaller diameter than the first bump. The first base layer has flat upper surface or first recess having depth of 20 μm or less in upper central portion. The second base layer has flat upper surface, raised portion in upper central portion, or second recess shallower than the first recess in the upper central portion.

A display apparatus, includes: a flexible circuit board including a first board pad and a second board pad, which are spaced apart from each other in a first direction and extend in a second direction intersecting the first direction; a main circuit board coupled to the flexible circuit board; and a display panel coupled to the flexible circuit board, the display panel including a first display pad overlapped with the first board pad and a second display pad overlapped with the second board pad, wherein the first board pad includes a first, second, and third portions, and the second board pad includes a first, second, and third portions.

A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.

Trace transfer techniques can be used to couple touch electrodes to touch sensing circuitry with a reduced border region around a touch sensor panel. Touch electrodes on a first side of the substrate can be routed to a bond pad region on the second side of the substrate via a trace transfer technique to enable single-sided bonding of a double-sided touch sensor panel. Trace transfer techniques can also be used to couple conductive traces on a first side of the substrate to a flex circuit oriented perpendicular to or otherwise not parallel to the first side of the substrate. Orienting the flex circuit in this way can allow the flex circuit to connect to touch circuitry with reduced bending as compared with the amount of bending of the flex circuit when oriented substantially parallel to the substrate.