Described examples include an apparatus, including: a substrate having a first surface configured to mount at least one integrated circuit and having a second surface opposite the first surface, the second surface having a plurality of terminals arranged in rows and columns, and at least one row of the plurality of terminals disposed adjacent a first side and extending generally along the length of the substrate arranged in a pattern extending along a longitudinal line, the pattern including a first group of consecutive terminals extending in a first direction at a first angle to the longitudinal line and directed towards an interior of the substrate, a second group of consecutive terminals extending in a second direction at a second angle and extending towards the periphery of the substrate, and a third group of consecutive ones of the terminals extending from the second group in the first direction.

A flat panel display device includes: a substrate including a display region and a non-display region disposed at the periphery of the display region; a plurality of pixels disposed in the display region of the substrate, the plurality of pixels displaying an image; a plurality of pads disposed in the non-display region of the substrate; and a plurality of connecting lines electrically connecting the plurality of pads to the plurality of pixels. The plurality of pads are disposed above the plurality of connecting lines, and are electrically connected to the plurality of connecting lines through contact holes formed in an insulating layer. At least one pad among the plurality of pads overlaps with another connecting line connected to an adjacent pad.

A bonding pad structure includes a substrate, a flexible printed circuit board, and a plurality of bonding pins. The bonding pins include at least one central bonding pin and at least two first bonding pins. The at least one central bonding pin is located at a center of bonding pins. The at least two first bonding pins are located farthest away from the at least one central bonding pin and have mirror symmetry with respect to the at least one central bonding pin. The at least one central bonding pin includes a first end and a second end. A first width A of the first end and a second width B of the second end satisfy 0<A/B≤1.

A tilt angle θ is formed between one of the at least two first bonding pins and one side of the substrate and satisfies 0<θ≤90.

A battery, for example, a rechargeable battery (e.g. lithium ion battery) having a casing with battery terminals. The casing, for example, includes an upper section, middle section, and lower section connected together. The battery can be connected to one or more battery trays having the same height or different heights for various applications.

A display device includes first power supply terminal electrodes and second power supply terminal electrodes. The first power supply terminal electrodes in a first terminal portion of a frame area at least partially overlap, in a plan view, at least a part of the second power supply terminal electrodes in a second terminal portion of a flexible printed board. The second power supply terminal electrodes are electrically connected to the first power supply terminal electrodes. Either the first power supply terminal electrodes or the second power supply terminal electrodes are inclined from the others.

A system and method for dissipating heat from a package and reducing interference between signaling pins is disclosed. The system includes a circuit substrate that includes a dielectric layer and at least one metal layer having an external surface. A plurality of metal posts is disposed on the external surface that function to a least one of dissipate heat from the circuit substrate, shield interfering signals between the signaling pins, and interact with mounting substrates on corresponding componentry. One or more metal posts are merged, increasing the interference shielding and heat dissipation functions of the metal posts.

Provided is an electronic component including a pad region including a plurality of pads extending along corresponding extension lines and arranged in a first direction, and a signal wire configured to receive a driving signal from the pad region, wherein the plurality of pads include a plurality of first pads arranged continuously and a plurality of second pads arranged continuously, and extension lines of the plurality of first pads substantially converge into a first point and extension lines of the plurality of second pads substantially converge into a second point different from the first point.

A printed circuit board includes: a base member, a first line and a second line disposed on the base member, and a plurality of pad portions disposed on the base member. Each of the plurality of pad portions includes: a first input pad and a second input pad connected to the first line, respectively, and which receives an electrical signal or voltage. Each of the plurality of pad portions includes a first output pad and a second output pad connected to the second line, respectively, and which provide the electrical signal or the voltage to a display panel.

An inverter with a modular bus assembly is described. In various embodiments, the modular bus assembly includes a laminated motherboard and a plurality of capacitor daughtercards. The laminated motherboard can be configured to interface a plurality of phase-leg modules and a plurality of capacitor daughtercards through a plurality of terminals and connectors located on a bottom side or a top side of the laminated motherboard. The laminated motherboard includes a layer stack with a plurality of conductor layers. Each of the plurality of conductor layers is implemented with a net spacing from a neighboring plated through hole (PTH) based at least in part on differences in potential to be applied to each of the plurality of conductor layers as compared to a potential to be applied to the PTH. Embedded shield polygons can be implemented on the laminated motherboard to mitigate surface discharge at surface terminal (PTH/SMT) triple junctions.