A display device includes a substrate, conductive pads arranged on the substrate over a plurality of rows, and a drive circuit chip including bumps arranged over a plurality of rows to be electrically connected with the conductive pads, and the conductive pads arranged in a same row are arranged in parallel, and the bumps arranged in a same row are arranged in a zigzag form so as to be partially shifted.

A method is presented that improves reliability for the mechanical electrical connection formed between a grid array device, such as a pin grid array device (PGA) or a column grid array device (CGA), and a substrate such as a printed circuit board (PCB). Between adjacent PCB pads, the method increases a spacing pattern toward the periphery of the CGA, creating a misalignment between pads and columns. As part of the method, columns align with the pads, resulting in column tilt that increases from the center to the periphery of the CGA. An advantage of the method is that the column tilt reduces the amount of contractions and expansions of columns during thermal cycling, thereby increasing the projected life of CGA. Another advantage of the method is that it reduces shear stress, further increasing the projected life of the CGA.

This application provides a multilayer printed circuit board (PCB). There is a pad array on a surface of the multilayer PCB. The pad array includes at least one padding unit, and each padding unit includes a first pad and a second pad that are adjacent. Both the first pad and the second pad are connected to a first Z-directed transmission line located in a Z-directed groove. In this way, to wire a signal wire on a signal layer of the multilayer PCB, a quantity of Z-directed grooves that need to be bypassed is less than a quantity of vias that need to be bypassed in the prior art. In other words, wiring of the signal wire is easier to some extent. In addition, this application further provides a corresponding communications device.

A semiconductor chip is mounted on a mounting substrate. The semiconductor chip includes plural first bumps on a surface facing the mounting substrate. The plural first bumps each have a shape elongated in a first direction in plan view and are arranged in a second direction perpendicular to the first direction. The mounting substrate includes, on a surface on which the semiconductor chip is mounted, at least one first land connected to the plural first bumps. At least two first bumps of the plural first bumps are connected to each first land. The difference between the dimension of the first land in the second direction and the distance between the outer edges of two first bumps at respective ends of the arranged first bumps connected to the first land is 20 m or less.

A printed circuit board includes an electronic component including a first land, a printed wiring board including a resist portion and a second land, and a connecting portion interconnecting the first land and the second land. An opening larger than the first land in plan view from the electronic component side is defined in the resist portion. In plan view from the electronic component side, the first land is disposed inside the opening, the second land including a body portion disposed inside the opening and a protruding portion protruding from the body portion, the body portion being disposed further on an inside than an outer edge of the first land, and at least part of the protruding portion protruding further to an outside than the first land.

An electronic device according to various embodiments may include: a board; a communication circuit disposed on one face of the board and configured to process a communication signal in a designated frequency band; an antenna disposed on the one face of the board or inside the board; a connector disposed on another face of the board, and including a first contact electrically connected to a first signal path through which the communication circuit is configured to transmit a signal to the antenna in a first direction, and a second contact electrically connected to a second signal path through which the communication circuit configured to transmit a signal to the antenna in a second direction; and conductive pads disposed on the another face of the board spaced apart from the connector, and including at least two first pads corresponding to the first contact and at least two second pads corresponding to the second contact.

A semiconductor device has a semiconductor die with a plurality of bumps formed over contact pads on a surface of the semiconductor die. The bumps can have a fusible portion and non-fusible portion. A plurality of conductive traces is formed over a substrate with interconnect sites having a width greater than 20% and less than 80% of a width of a contact interface between the bumps and contact pads. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate. The conductive traces have a pitch as determined by minimum spacing between adjacent conductive traces that can be placed on the substrate and the width of the interconnect site provides a routing density equal to the pitch of the conductive traces.

A multilayer electronic component includes a capacitor body including a plurality of dielectric layers and a plurality of first and second internal electrodes and having first to sixth surfaces, the first and second internal electrodes being exposed through the third and fourth surfaces, respectively; first and second external electrodes including first and second connected portions respectively disposed on the third and fourth surfaces of the capacitor body and first and second band portions respectively extending from the first and second connected portions to portions of the first surface of the capacitor body, respectively; a first connection terminal disposed on the first band portion; and a second connection terminal disposed on the second band portion, wherein 0.05A1/A10.504, where A1 is an area of the first or second connection terminal in a thickness-width direction, and A2 is an area of the first or second band portion in a width-length direction.

An electronic device including: a discrete transistor including a semiconductor chip encapsulated in a package made of an insulating material leaving access to a first pad of connection to a first conduction terminal of the transistor; and a printed circuit board (320) including first (125) and second (129) separate connection pads, wherein the transistor is assembled on the printed circuit board so that the first connection pad (105) of the transistor is in contact with the first (125) and second (129) connection pads of the printed circuit board.

The invention concerns a discrete electronic component including: a semiconductor chip including a transistor, the chip including a first metallization of connection to a first conduction region of the transistor; and a printed circuit board including first and second separate connection pads, wherein: the chip is assembled on the printed circuit board so that the first metallization of the chip is in contact with the first and second connection pads of the printed circuit board; and the assembly including the semiconductor chip and the printed circuit board is encapsulated in a package made of an insulating material leaving access to first and second connection terminals of the component connected, inside of the package, respectively to the first and second connection pads of the printed circuit board.