A component carrier with a stack including at least one electrically insulating layer structure and at least one electrically insulating structure has a tapering blind hole formed in the stack and an electrically conductive plating layer extending along at least part of a horizontal surface of the stack outside of the blind hole and along at least part of a surface of the blind hole. A minimum thickness of the plating layer at a bottom of the blind hole is at least 8 μm.

A voltage regulator module includes a first circuit board assembly and a signal communication part. The first circuit board assembly includes a plurality of first conduction pads. The signal communication part is arranged on the first circuit board assembly. The signal communication part includes a conduction circuit board with a plurality of conduction fingers and a plurality of surface pins. The plurality of conduction fingers are formed on at least one lateral side of the conduction circuit board. The plurality of surface pins are electroplated on a top side and a bottom side of the conduction circuit board. A first end of each conduction finger is contacted with the corresponding surface pin on the top side. A second end of each conduction finger is contacted with the corresponding surface pin on the bottom side. The signal communication part is fixed on and electrically connected with the first circuit board assembly.

A component carrier is disclosed. The component carrier includes: i) at least one electrically insulating layer structure and at least one electrically conductive layer structure, wherein the electrically conductive layer structure is formed in or below the electrically insulating layer structure, and ii) a laser via formed in the electrically insulating layer structure and extending down to the electrically conductive layer structure, wherein the laser via is at least partially filled with an electrically conductive material. Hereby, a connection diameter at a first end of the laser via at the electrically conductive layer structure is equal to or larger than an opening diameter at a second end of the laser via facing away from the electrically conductive layer structure.

An object here is to provide a control device which can be reduced in size, weight and cost while being able to prevent unauthorized access. The control device includes: a microcontroller having a storage device, a processor, a package in which the storage device and the processor are accommodated, and multiple communication electrodes provided on a bottom surface of the package; and a wiring board having wiring layers comprised of a front surface layer, an intermediate layer and a rear surface layer, each having a wiring pattern formed therein, insulating members for insulating the respective wiring layers from each other; interlayer connection portions each making an electrical connection between the wiring patterns in different ones of the wiring layers; multiple electrode pads formed n the front surface layer; and communication-dedicated interlayer connection portions which are electrically connected to the respective electrode pads, and which are each externally exposed.

An interconnect structure for a redistribution layer includes an intermediate via land pad; a cluster of upper conductive vias abutting the intermediate via land pad and electrically coupling the intermediate via land pad to an upper via land pad; and an array of lower conductive vias electrically coupling the intermediate via land pad with a lower circuit pad. The array of lower conductive vias is arranged within a horseshoe-shaped via array region extending along a perimeter of the intermediate via land pad. The array of lower conductive vias arranged within the horseshoe-shaped via array region does not overlap with the cluster of upper conductive vias.

A printed circuit board (PCB) core structure is provided for the transition of signals from one side of a PCB to an opposing side of the PCB. The PCB core structure may include a laminated core including an inner core including a plurality of conductive layers (N layers), a first dielectric layer, a first conductive trace disposed over the Nth conductive layer on a first side of the laminated core. The PCB core structure may also include a signal via extending from a first conductive layer to an Nth conductive layer through the laminated core, the signal via configured to connect the first conductive trace to a pin or a second conductive trace on a second side of the laminated core. The PCB core structure may also include a shielding structure surrounding the signal via and partially extending from the first conductive layer to the Nth conductive layer. The PCB core structure may also include a cavity removing a portion of the shielding structure in the Nth conductive layer and filled with a dielectric material. The cavity filled with the dielectric material prevents the first conductive trace from shorting to the shielding structure. The PCB core structure may be fabricated by using a single-lamination cycle.

A circuit board includes a conductive metal layer, at least one insulating layer, at least one thermally conductive insulating layer and a heat dissipation element. The conductive metal layer is mainly used to transmit electronic signals. The insulating layer is connected to the conductive metal layer. The thermally conductive insulating layer is sandwiched between the conductive metal layer and the insulating layer, and thermally contacts the conductive metal layer, and is used for thermally conducting the heat of the conductive metal layer. The heat dissipation element is in thermal contact with the thermally conductive insulating layer, and is used to conduct the heat of the thermally conductive insulating layer to the outside through a heat dissipation channel.

A radio frequency front-end module, a manufacturing method thereof and a communication device are provided. The radio frequency front-end module includes a first base substrate and a metal bonding structure; a second functional substrate, including a second base substrate, a groove in the second base substrate, and a bonding metal layer; and a first radio frequency front-end component, at least partially located in the groove, the first base substrate and the second base substrate are oppositely arranged, and a surface of the second base substrate close to the first base substrate includes a groove surface inside the groove and a substrate surface outside the groove, and the bonding metal layer includes a first metal portion located on the groove surface and a second metal portion located on the substrate surface, the first radio frequency front-end component is at least partially surrounded by the first metal portion.

A circuit board structure includes a first dielectric layer, first and second inner circuit layers, a conductive connection layer, a second dielectric layer, two third dielectric layers, third and fourth inner circuit layers, two conductive through vias, first and second annular retaining walls, two fourth dielectric layers, first and second external circuit layers, and third and fourth annular retaining walls. The conductive through vias penetrate the third and second dielectric layers and electrically connect the third and fourth inner circuit layers. The first and second annular retaining walls surround the conductive through vias and electrically connect the third and first and the fourth and second inner circuit layers. The third and fourth annular retaining walls are respectively disposed in the fourth dielectric layers and electrically connect the first external circuit layer and the third inner circuit layer and the second external circuit layer and the fourth inner circuit layer.

A circuit board structure includes a substrate, a third dielectric layer, a fourth dielectric layer, a first external circuit layer, a second external circuit layer, a conductive through hole, a first annular retaining wall, and a second annular retaining wall. The conductive through hole penetrates through the third dielectric layer, a second dielectric layer, and the fourth dielectric layer. The conductive through hole is electrically connected to the first external circuit layer and the second external circuit layer. The first annular retaining wall is disposed in the third dielectric layer, surrounds the conductive through hole, and is electrically connected to the first external circuit layer and the first inner circuit layer. The second annular retaining wall is disposed in the fourth dielectric layer, surrounds the conductive through hole, and connects to the second external circuit layer and the second inner circuit layer electrically.