A method for producing a flexible printed circuit board according to an embodiment of the present invention includes a through-hole formation step of preparing a base material including a base film having insulating properties and flexibility and a pair of metal films stacked on both surface sides of the base film, and forming a through-hole in the metal film on a front surface side of the base material and the base film; a filling step of stacking, by electroplating on a front surface of the base material, stacking a conductive material on a surface of the metal film on the front surface side to form a conductive material layer and to fill the through-hole with the conductive material; and a removal step of removing, by etching the front surface of the base material, a surface layer of the conductive material layer stacked on the surface of the metal film on the front surface side and a surface layer of the conductive material filling the through-hole.

A high-speed transmission circuit design reduces or eliminates the presence of unwanted stub-effects and avoids uncontrolled line impedances that in existing circuits cause impedance mismatches that give rise to unwanted reflections and, ultimately, degrade signal integrity, e.g., in belly-to-belly configurations involving Quad Small Form-Factor Pluggable Double Density (QSFP DD) connectors. In various embodiments, by preventing overcrowding of signal lines, the circuit design further reduces crosstalk and increases signal integrity.

A wiring board includes a photosensitive insulating layer and a first wiring layer. The photosensitive insulating layer has a hole, a first surface and a second surface opposite to each other. The hole has a first end opening formed in the first surface, a second end opening formed in the second surface, an axis, and a sidewall surrounding the axis. Part of the sidewall extends toward the axis to form at least one annular flange. The first wiring layer is disposed on the first surface and includes a first pad, in which the hole exposes the first pad. There is at least one recessed cavity between the annular flange and the first pad. The minimum width of the annular flange is smaller than the maximum width of the recessed cavity.

An apparatus includes a first circuit board, a driving chip, and a second circuit board. The driving chip is coupled to the first circuit board, and the second circuit board is spaced apart from and electrically connected to the driving chip. At least part of the second circuit board is spaced apart from a first surface of the first circuit board.

A package that includes a substrate and an electrical component coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects located in the at least one dielectric layer, and a solder resist layer located over a surface of the at least one dielectric layer. The solder resist layer includes a first solder resist layer portion comprising a first thickness, and a second solder resist layer portion comprising a second thickness that is less than the first thickness. The electrical component is located over the second solder resist layer portion.

A semiconductor chip module includes a PCB including first and second faces; a buffer on the first face; a first chip on the first face, and including a first connection terminal and a second connection terminal, a first signal being provided to the first connection terminal, and a second signal being provided to the second connection terminal; a second chip on the second face, and including a third connection terminal to which the first signal is provided, and a fourth connection terminal to which the second signal is provided. The first connection terminal and the third connection terminal may receive the first signal from the buffer at the same time. The first connection terminal may be closer to the buffer as compared with the second connection terminal. The third connection terminal may be closer to the buffer as compared with the fourth connection terminal.

A carrier comprises: a main body made of a material comprising a thermal conductivity of at least 380 W/(m K), wherein the main body comprises a mounting surface for mechanical and thermal connection with a component, wherein the main body comprises a recess which penetrates the main body along a first direction perpendicular to the main extension plane of the main body, an electrically insulating filler is arranged in the recess, which comprises a further recess penetrating the filler along the first direction, an inner wall of the filler surrounding the further recess is provided with an electrically conductive coating to form a via through the main body.

A printed circuit board (PCB) device including one or more insulating layers and one or more conducting layers arranged to form a layer stack; and one or more blind holes disposed along a side edge of the layer stack and parallel to a plane of the layer stack. Each of the one or more blind holes along the side edge of the layer stack is configured to receive a pin. Each pin can make an electrical connection with a corresponding blind hole.

A drive backboard includes: a first conductive layer including bonding pins and first connecting lines, an insulating layer including first via holes and second via holes, a second conductive layer including connecting electrodes and second connecting lines and a conductive protective layer including first protective structures and second protective structures. The first via hole exposes the bonding pin, one end of a first connecting line electrically connects a bonding pin, and the other end reaches the second via hole. One end of a second connecting line electrically connects a connecting electrode, and the other end electrically connects the first connecting line through the second via hole. The first protective structure covers the bonding pin, and the second protective structure covers the second connecting line formed at the position of the second via hole. The pattern of the conductive protective layer is complementary to the pattern of the insulating layer.

An active chip package substrate and a method for preparing the same. The active chip package substrate includes: a core board; at least one upper active chip, embedded in the core board and having an active surface facing toward a lower surface of the core board, the upper active chip being an active bare chip; and at least one lower active chip, embedded in the core board and having an active surface facing toward an upper surface of the core board, the lower active chip being an active bare chip.