A wiring substrate includes: a base material; a first through-hole and a second through-hole that are formed in the base material; magnetic material that is filled in the first through-hole; a third through-hole that is formed in the magnetic material; a first plating film that covers an inner wall surface of the third through-hole; and a second plating film that covers an inner wall surface of the second through-hole and the first plating film. The first plating film includes a first electroless plating film that is in contact with the inner wall surface of the third through-hole, and a first electrolytic plating film that is laminated on the first electroless plating film.

A pressure sensor and an electronic device are disclosed. The pressure sensor includes a flexible printed circuit board (110) and multiple pressure sensitive adhesive resistors. The multiple pressure sensitive adhesive resistors include pressure sensitive adhesive resistors R1, R2, R3, R4, R5, and R6. The flexible printed circuit board (110) includes a first surface (A) and a second surface (B) that are opposite each other. The pressure sensitive adhesive resistors R1, R3, and R5 are disposed on the first surface (A), and the pressure sensitive adhesive resistors R2, R4, and R6 are disposed on the second surface (B). The flexible printed circuit board (110) is provided with a through hole (C) that allows the first surface (A) to communicate with the second surface (B), and the through hole (C) is at least partially covered by the pressure sensitive adhesive resistors R1, R2, R3, and R4.

The present invention provides a novel method of constructing a coax spring-pin socket that furnishes better performance and is easier to manufacture in volume using common dielectrics and copper plating. This is accomplished by, in application, a lamination of PCB dielectric layers. This dielectric block is then drilled, plated, etched, and drilled in steps for the construction of a coaxial structure for the signal pins, and a ground structure for ground pins. This design process that can be quickly adjusted and customized for each design.

A passive device packaging structure embedded in a glass medium according to an embodiment of the present disclosures includes a glass substrate and at least one capacitor embedded in the glass substrate. The capacitor includes an upper electrode, a dielectric layer, and a lower electrode. The glass substrate is provided on its upper surface with a cavity, the dielectric layer covers a surface of the cavity and has an area larger than that of the cavity. The upper electrode is provided on the dielectric layer. The dielectric layer and the lower electrode are connected by a metal via pillar passing through the glass substrate.

A semiconductor module includes a printed circuit board including an integrated circuit chip, connecting terminals at an edge of the printed circuit board, and signal lines respectively connecting electrical connection pads of the integrated circuit chip to the connecting terminals. The connecting terminals are plated using via-holes of the printed circuit board respectively connected to the signal lines.

A circuit board includes: a first surface and a second surface opposite to the first surface; a through hole extending between the first surface and the second surface; a conductor covering an inner wall surface of the through hole, a first end and a second end of the conductor being terminated inside the through hole; and a wire connected to the conductor, wherein a sum of a length from a contact portion where the conductor contacts a connector pin inserted in the through hole to the first end of the conductor, and a length from a wire connecting portion where the conductor is connected to the wire to the second end of the conductor is 0.5 mm or less.

A passive device packaging structure embedded in a glass medium according to an embodiment of the present disclosures includes a glass substrate and at least one capacitor embedded in the glass substrate. The capacitor includes an upper electrode, a dielectric layer, and a lower electrode. The glass substrate is provided on its upper surface with a cavity, the dielectric layer covers a surface of the cavity and has an area larger than that of the cavity. The upper electrode is provided on the dielectric layer. The dielectric layer and the lower electrode are connected by a metal via pillar passing through the glass substrate.

A method for manufacturing an interconnect structure and an interconnect structure are provided. The method includes: forming an opening in a substrate; forming a low-k dielectric block in the opening; forming at least one via in the low-k dielectric block; and forming a conductor in the via. The interconnect structure includes a substrate, a dielectric block, and a conductor. The substrate has an opening therein. The dielectric block is present in the opening of the substrate. The dielectric block has at least one via therein. The dielectric block has a dielectric constant smaller than that of the substrate. The conductor is present in the via of the dielectric block.

A printed circuit board includes a plurality of layers including attachment layers and routing layers; first and second signal vias forming a differential signal pair, the first and second signal vias extending through the attachment layers and connecting to respective signal traces on a breakout layer of the routing layers; an antipad of a first type around and between the first and second signal vias in one or more of the attachment layers; and antipads of a second type around the first and second signal vias in at least one routing layer adjacent to the breakout layer.

An interconnect structure includes a substrate, a dielectric block, and a conductor. The dielectric block is in the substrate. A dielectric constant of the dielectric block is smaller than a dielectric constant of the substrate, and the dielectric block and the substrate have substantially the same thickness. The conductor includes a first portion extending from a top surface to a bottom surface of the dielectric block and a second portion extending along and contacting the top surface of the dielectric block.