A wiring structure includes a first dielectric layer, a second dielectric layer adjacent to the first dielectric layer, and a conductive region. The first dielectric layer defines a first opening, and the second dielectric layer defines a second opening. The conductive region includes a conductive via filling the first opening and the second opening. The conductive region further includes a first conductive trace embedded in the second dielectric layer and electrically connected with the conductive via. The conductive region includes a sidewall traversing through a thickness of the second dielectric layer with a substantial linear profile. A method of manufacturing a wiring structure is also disclosed.

A wiring structure includes a first dielectric layer, a second dielectric layer adjacent to the first dielectric layer, and a conductive region. The first dielectric layer defines a first opening, and the second dielectric layer defines a second opening. The conductive region includes a conductive via filling the first opening and the second opening. The conductive region further includes a first conductive trace embedded in the second dielectric layer and electrically connected with the conductive via. The conductive region includes a sidewall traversing through a thickness of the second dielectric layer with a substantial linear profile. A method of manufacturing a wiring structure is also disclosed.

A method and a system for detecting defects in plated-through hole by partially submerging a printed circuit board in a fluid bath. The method includes partially submerging a printed circuit board on a first side and measuring a capillary height difference within a plated-through hole and the surrounding fluid bath. The method further includes partially submerging the printed circuit board on a second side and measuring a second capillary height difference within the plated-through hole and the surrounding fluid bath. The method also includes comparing the measured values with predetermined values to determine the quality of the plated-through hole.

A component carrier includes a stack with a plurality of electrically conductive layer structures and at least one electrically insulating layer structure. The electrically conductive layer structures include an electrically conductive vertical through-connection and a horizontally extending electrically conductive trace electrically coupled with an end portion of the vertical through-connection. A back-drill hole extends through at least part of the at least one electrically insulating layer structure towards the end portion of the vertical through-connection. An etching neck connects the back-drill hole with the end portion of the vertical through-connection.

A wiring substrate includes a first insulating layer, a first conductor layer, and a plurality of filled vias. The first insulating layer has a first surface and a second surface positioned on a side opposite to the first surface. The first conductor layer is formed on the first surface of the first insulating layer. The plurality of filled vias are formed inside the first insulating layer. The plurality of filled vias each have a structure in which a via hole penetrating the first insulating layer is filled with a metal. The first conductor layer includes a pad. The pad overlaps the plurality of filled vias in a plan view from a thickness direction of the first insulating layer and is connected to the plurality of filled vias.

The present disclosure is directed to a printed circuit board having a first surface and providing a signal pathway using a plurality of plated through hole (PTH) vias including a first set of PTH vias having a first PTH via coupled to a second PTH via and a first vertical separator being configured therebetween, with the first vertical separator extending a first depth from the first surface, and a second set of PTH vias having a third PTH via coupled to a fourth PTH via and a second vertical separator being configured therebetween, with the second vertical separator extending a second depth from the first surface, and a connector trace coupling the second PTH via to the third PTH via being positioned at a third depth from the first surface, for which the third depth is less than the first depth or the second depth.

An interconnect structure includes a substrate, a dielectric block, and a conductor. The dielectric block is in the substrate. A dielectric constant of the dielectric block is smaller than a dielectric constant of the substrate, and the dielectric block and the substrate have substantially the same thickness. The conductor includes a first portion extending from a top surface to a bottom surface of the dielectric block and a second portion extending along and contacting the top surface of the dielectric block.

A circuit board includes a baseboard, a first conductive circuit layer, a second conductive circuit layer, at least one through hole, and a number of conductive lines. The first conductive circuit layer includes a number of first conductive circuit lines formed on a first side of the baseboard. The second conductive circuit layer includes a number of second conductive circuit lines formed on a second side of the baseboard. The through hole is defined through the first conductive circuit layer, the baseboard, and the second conductive circuit layer. The number of conductive lines are formed in an inner wall of the through hole and spaced apart around the through hole. Each conductive line electrically couples one of the first conductive circuit lines to a corresponding one of the second conductive circuit lines.

A printed wiring board includes an insulator having a first surface, and a second surface opposite to the first surface, and including a through-hole penetrating from the first surface to the second surface, and a metal plated layer formed on the first surface and the second surface of the insulator, and on an inner peripheral surface of the through-hole, wherein an inside diameter of the through-hole gradually decreases from the first surface toward the second surface of the insulator, an average diameter of the through-hole at the first surface of the insulator is 20 m or greater and 35 m or less, the average diameter of the through-hole at the second surface of the insulator is 3 m or greater and 15 m or less, and an average thickness of the metal plated layer formed on the first surface and the second surface of the insulator is 8 m or greater and 12 m or less.

A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.