A component carrier includes a stack having at least one horizontal electrically conductive layer structure, at least one electrically insulating layer structure, a semiconductor component embedded in the stack, and at least one vertical via being laterally offset from the semiconductor component. The at least one horizontal electrically conductive layer structure electrically connects the vertical via to a bottom main surface of the semiconductor component. The component carrier is configured for a current flow from the vertical via to the horizontal electrically conductive layer structure, from the horizontal electrically conductive layer structure to the bottom main surface of the semiconductor component, from the bottom main surface of the semiconductor component to an upper main surface of the semiconductor component, and from the upper surface of the semiconductor component to the outside of the component carrier.

A wiring substrate includes a first insulating layer, a conductor layer formed on the first insulating layer, a second insulating layer formed on the first insulating layer such that the second insulating layer is covering the conductor layer, and a coating film formed on a surface of the conductor layer such that the coating film is adhering the conductor layer and the second insulating layer. The conductor layer includes a conductor pad and a wiring pattern, and the conductor pad of the conductor layer has a mounting surface including a first region and a component mounting region formed such that the second insulating layer has a through hole exposing the component mounting region and that the first region is covered by the second insulating layer and roughened to have a surface roughness higher than a first surface roughness of a surface of the wiring pattern facing the second insulating layer.

A printed circuit board includes a plurality of layers including attachment layers and routing layers; and columns of via patterns formed in the plurality of layers, wherein via patterns in adjacent columns are offset in a direction of the columns, each of the via patterns comprising: first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; and at least one conductive shadow via located between the first and second signal vias of the differential pair. In some embodiments, at least one conductive shadow via is electrically connected to a conductive surface film.

A wiring board includes an insulating base having a first principal surface, and a second principal surface opposite to the first principal surface, a first through hole formed in the base, a first conductive layer provided inside the first through hole, a first insulating layer covering the first principal surface, a second insulating layer covering the second principal surface, a second through hole formed in the first insulating layer, the base, and the second insulating layer, a magnetic material provided inside the second through hole, a third through hole famed in the magnetic material, and a second conductive layer provided inside the third through hole.

Proposed are a multilayer wiring board having both durability and chemical resistance, and a probe card including the same.

A component carrier includes a stack with at least one electrically conductive layer structure and at least one electrically insulating layer structure. At least one electrically insulating layer structure has at least partly tapering through holes filled substantially completely with an electrically conductive filling. The at least one electrically conductive layer structure and the electrically conductive filling are made of the same material. In addition, different ones of the through holes of one electrically insulating layer structure are tapering in opposite directions.

A wiring substrate includes a first insulating layer, a first conductor layer, a second insulating layer, a second conductor layer, a connection conductor, and a coating film. The first conductor layer includes a conductor pad and a wiring pattern such that the conductor pad is formed in contact with the connection conductor and that the wiring pattern is covered by the coating film, the conductor pad has a surface facing the second insulating layer and having first surface roughness higher than surface roughness of a surface of the wiring pattern, and the coating film has opening exposing a portion of the surface of the conductor pad from the coating film and having area larger than area of interface between the conductor pad and the connection conductor and that the connection conductor is formed on the portion of the surface of the conductor pad and is separated from the coating film.

An electronic device with high density for component arrangement includes a first substrate, a second substrate, a plural of passages formed through the first and the second substrates, a first contact arranged on the first face of the first substrate to conceal the corresponding one of the passages, a second contact arranged on the second substrate and adjacent to the corresponding one of the passages, and a conductor disposed in the passages. A first end of the conductor electrically connects the first contact, while a second end of the conductor electrically connects the second contact.

Embodiments described herein may be related to apparatuses, processes, and techniques directed to embedding capacitors in through glass vias within a glass core of a substrate. In embodiments, the through glass vias may extend entirely from a first side of the glass core to a second side of the glass core opposite the first side. Layers of electrically conductive material and dielectric material may then be deposited within the through glass via to form a capacitor. the capacitor may then be electrically coupled with electrical routings on buildup layers on either side of the glass core. Other embodiments may be described and/or claimed.

A component carrier includes (a) a first stack with at least one first electrically conductive layer structure and/or at least one first electrically insulating layer structure; (b) a hole formed within the first stack; and (c) a non-deformable solid body closing a portion of the hole and being spaced with respect to side walls of the hole by a gap. A component carrier assembly includes (a) a component carrier as described above; (b) a second stack having at least one second electrically conductive layer structure and/or at least one second electrically insulating layer structure; and (c) a connection piece connecting the first stack with the second stack. Further described are methods for manufacturing such a component carrier and such a component carrier assembly.