A wiring substrate includes a first conductor layer including wirings, an interlayer insulating layer formed on and covering the first conductor layer, a wiring layer formed in the interlayer insulating layer and including wirings, a second conductor layer formed on the interlayer insulating layer and including wirings, and a via conductor formed in the interlayer insulating layer such that the via conductor is penetrating through the interlayer insulating layer and connecting the first and second conductor layers. The interlayer insulating layer includes first and second insulating layers such that the wiring layer is formed on a surface of the first insulating layer, and the wiring layer is formed such that an aspect ratio of the wirings in the wiring layer is in the range of 2.0 to 6.0 and that aspect ratios of the wirings in the first and second conductor layers are in the range of 1.0 to 2.0.

A wiring substrate includes a first conductor layer including wirings, an interlayer insulating layer formed on the first conductor layer and covering the first conductor layer, a second conductor layer formed on the interlayer insulating layer and including wirings, a via conductor formed in the interlayer insulating layer such that the via conductor is penetrating through the interlayer insulating layer and connecting the first conductor layer and the second conductor layer, and a wiring part formed in the interlayer insulating layer and including an embedded wiring layer filling one or more grooves formed in the interlayer insulating layer. The interlayer insulating layer includes a first insulating layer and a second insulating layer laminated on the first insulating layer, and the embedded wiring layer is formed in the first insulating layer on a side facing the second insulating layer and filling the groove or grooves formed in the first insulating layer.

A printed circuit board (PCB) includes a substrate including a first insulating layer and first wiring patterns disposed on the first insulating layer, an optical sensing chip including a vertical cavity surface emitting laser (VCSEL) and a photodiode, disposed on the first insulating layer to be in contact with at least one of the first wiring patterns, a transimpedance amplifier (TIA) chip disposed to be spaced apart from the optical sensing chip on the first insulating layer and disposed to be in contact with at least one first wiring pattern, different from the first wiring pattern connected to the optical sensing chip, among the first wiring patterns, and a dielectric layer stacked on the substrate and having a hole exposing the VCSEL and the photodiode of the optical sensing chip. The optical sensing chip and the transimpedance amplifier chip are connected through a wiring pattern disposed on the dielectric layer.

A printed circuit board and a method of manufacturing the same are provided. The printed circuit board includes a wiring substrate including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers and having a cavity penetrating through a portion of the plurality of insulating layers, a passive component disposed in the cavity and including an external electrode electrically connected to at least one of the plurality of wiring layers, and a bridge disposed on the passive component in the cavity and including one or more circuit layers electrically connected to the external electrode.

A resin multilayer substrate includes a multilayer body including resin layers and adhesive layers that are laminated, via conductors in the resin layers, and bonding portions in the adhesive layers. The bonding portion is connected to the via conductor. One of the resin layer and the adhesive layer is a gas high-permeable layer having a higher gas permeability than the other one. The bonding portion includes an organic substance, or has a higher void content rate per unit plane sectional area than the via conductor. At least a portion of each of the bonding portions contacts the gas high-permeable layers.

A printed circuit board according to an embodiment includes: a first insulating portion having a cavity; a second insulating portion disposed on the first insulating portion; a third insulating portion disposed under the first insulating portion; and an electronic device disposed in the cavity, wherein a number of layers of the second insulating portion is different from a number of layers of the third insulating portion, and has an asymmetric structure with respect to the first insulating portion in which the electronic device is disposed.

A multilayer wiring board includes a first insulating layer, a second insulating layer stacked on the first insulating layer, a via conductor inside each of the first insulating layer and the second insulating layer, and a conductive bonding layer that bonds the via conductors to each other. The first insulating layer is directly bonded to the second insulating layer, and a relationship a.sub.1>b.sub.1 is satisfied, where a.sub.1 is a maximum diameter of the bonding layer and b.sub.1 is a maximum diameter of the via conductor at an interface with the bonding layer.

A multilayer substrate includes a plurality of insulator layers laminated, a column conductor extending through two or more insulator layers among the plurality of insulator layers. The column conductor includes a first via conductor extending through a first insulator layer and a second via conductor extending through a second insulator layer adjacent to the first insulator layer. Each of the first via conductor and the second via conductor has a tapered shape in which a cross section decreases from one end portion to the other end portion in the lamination direction of the plurality of insulator layers. The first via conductor and the second via conductor are directly bonded to each other at large diameter portions that are end portions with a large cross section or small diameter portions that are end portions with a small cross section.

A resin multilayer substrate includes a plurality of insulating resin base material layers and a plurality of conductor patterns provided on the plurality of insulating resin base material layers. The plurality of conductor patterns include a signal line and a ground conductor overlapping the signal line as viewed from a laminating direction of the insulating resin base material layers. A plurality of openings are provided in the ground conductor, and an aperture ratio is higher in a zone far from the signal line than in a zone adjacent to or in a vicinity of the signal line in a direction perpendicular or substantially perpendicular to the laminating direction.

A method of manufacturing a component carrier includes (i) forming a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; (ii) assembling a component to the stack; and (iii) forming a thermally conductive tongue having an embedded portion embedded in the stack and having an exposed portion protruding beyond the stack, where a first width of the tongue in the embedded portion is different from a second width of the tongue in the exposed portion. A corresponding component carrier includes analogous features.