A wiring substrate includes an insulating layer, and a conductor layer formed on the insulating layer and including a mesh-like conductor pattern and conductor pads such that the mesh-like conductor pattern has openings exposing the insulating layer and that the conductor pads are formed at substantially centers of selected ones or all of the openings respectively. The conductor layer is formed such that each of the openings has a polygonal shape, that gaps are formed between the conductor pads and the conductor pattern surrounding the conductor pads, and that each of the conductor pads has a curved outer edge.

A circuit board includes an insulating material; and a heat-transfer structure comprising a plurality of heat-dissipating members and inserted in the insulating material, wherein the plurality of heat-dissipating members each includes a metal wire; and an insulating part disposed on an outer circumferential surface of the metal wire excluding a top surface and a bottom surface of the metal wire.

A circuit board includes: a first surface and a second surface opposite to the first surface; a through hole extending between the first surface and the second surface; a conductor covering an inner wall surface of the through hole, a first end and a second end of the conductor being terminated inside the through hole; and a wire connected to the conductor, wherein a sum of a length from a contact portion where the conductor contacts a connector pin inserted in the through hole to the first end of the conductor, and a length from a wire connecting portion where the conductor is connected to the wire to the second end of the conductor is 0.5 mm or less.

A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

A wiring board includes a core layer having a first through hole formed therein, a magnetic resin filled inside the first through hole, a second through hole formed in the magnetic resin, and a plating film covering an inner wall surface of the second through hole. The plating film includes an electroless plating film, and an electrolytic plating film. The electroless plating film makes direct contact with an inner wall surface of the second through hole.

A method for producing a printed circuit board (13, 15, 16) with multilayer subareas in sections, characterized by the following steps: a) providing at least one conducting foil (1, 1′) and application of a dielectric insulating foil (3, 3′) to at least one subarea of the conducting foil; b) applying a structure of conducting paths (4, 4′) to the insulating layer (3, 3′); c) providing one further printed circuit board structure; d) joining of the further printed circuit board structure with the conducting foil (1, 1′) plus insulating layer (3, 3′) and conducting paths (4, 4′) by interposing a prepreg layer (5, 85; 18, 18′), and e) laminating the parts joined in step d) under pressing pressure and heat; and a printed circuit board produced according to this method.

A resin multilayer board includes an insulating substrate including a first main surface and mounting electrodes only on the first main surface. The insulating substrate includes first and second resin layers that are laminated. The Young's modulus of the second resin layers is higher than that of the first resin layers. The first and second resin layers are arranged in a distributed manner along a lamination direction of the first and second resin layers. The insulating substrate includes a first and second portions that are two equally divided portions of the insulating substrate in the lamination direction and are respectively positioned closer to the first main surface and farther from the first main surface, and a volume ratio of the second resin layers in the first portion is higher than a volume ratio of the second resin layers in the second portion.

A stub of a via formed in a printed circuit board is backdrilled to a predetermined depth. A capacitance probe is positioned within the via. Then the capacitance probe is used to obtain a test capacitance measurement. The test capacitance measurement is compared to a predetermined baseline capacitance measurement. Residual conductive plating material in the backdrilled stub causes the test capacitance measurement to exceed the predetermined baseline capacitance measurement. An indication is made that the predetermined baseline capacitance measurement has been exceeded.

In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Systems and methods of manufacturing printed circuit boards using blind and internal micro vias to couple subassemblies. An embodiment of the invention provides a method of manufacturing a printed circuit including attaching a plurality of metal layer carriers to form a first subassembly including at least one copper foil pad on a first surface, applying an encapsulation material onto the first surface of the first subassembly, curing the encapsulation material and the first subassembly; applying a lamination adhesive to a surface of the cured encapsulation material, forming at least one via in the lamination adhesive and the cured encapsulation material to expose the at least one copper foil pad, attaching a plurality of metal layer carriers to form a second subassembly, and attaching the first subassembly and the second subassembly.