A printed circuit board having multiple layers of circuitry, the printed circuit board including a first layer having a first cylindrical opening with a first diameter, the first cylindrical opening formed through at least the first layer and formed about a particular axis; and a second layer having a second cylindrical opening with a second diameter, the second cylindrical opening formed through at least the second layer and formed about the particular axis, where the first cylindrical opening is a portion of a conductive via, and where the second diameter is smaller than the first diameter.

An electronic device may comprise a printed circuit board (PCB) and a power source and processing circuitry mounted to the PCB. The PCB comprises one or more power planes and a plurality of power vias electrically connected to the power planes. The power sources are electrically connected to the power planes. The processing circuitry is electrically connected to the plurality of power vias through a plurality of interconnects. Respective diameters of the plurality of power vias vary based on location.

A printed circuit board includes a connector insertion area including many rows of crimping holes, each row of crimping holes includes at least two pairs of signal crimping holes (SCHs), and each pair of SCHs includes two SCHs. In a row arrangement direction of the crimping holes, at least one ground crimping hole (GCH) is arranged on either side of each pair of SCHs. A depth of the GCH is greater than or equal to a depth of the SCH, the GCH includes a main hole and a shielding component on at least one side of the main hole, a part of a side wall of the main hole is a part of a side wall of the shielding component, and a sum of lengths of the main hole and the shielding component in a first direction is greater than a length of the SCHs in the first direction.

A substrate on which an electronic component is soldered, includes an electronic component, a through hole positioned on the substrate and passing through the substrate, a solder that joins the through hole and a terminal of the electronic component inserted in the through hole, a pattern formed on a first surface of the substrate, the first surface facing a second surface on which the electronic component is placed, a first resist superimposed on the pattern, an exposed portion of which the pattern is exposed from the first resist around the through hole, and a second resist superimposed on the pattern and arranged between the through hole and the exposed portion.

A method of forming an multi-chip carrier that includes providing a trace structure using an additive forming method. The method includes forming a metal layer on a trace structure to provide electrically conductive lines. A dielectric material may then be formed on the electrically conductive lines to encapsulate a majority of the electrically conductive lines. The ends of the electrically conductive lines that are exposed through the upper surface of the dielectric material provide a top processor mount location and the ends of the electrically conductive lines that are exposed through the sidewalls of the dielectric material provide a sidewall processor mount location.

Some embodiments relate to micro vias in printed circuit boards (PCBs). In an example, a PCB may include a PCB substrate and a micro via. The micro via may extend between opposing surfaces of the PCB substrate and may have a diameter less than or equal to about 100 microns. In another example, a method of forming micro vias in a PCB may include forming a through hole in a PCB substrate of the PCB. The method may also include positioning a pillar that is electrically conductive within the through hole. The method may also include backfilling the through hole around the pillar with an epoxy backfill.

A component carrier includes a first level stack of first plural of electrically conductive layer structures and/or first electrically insulating layer structures; a first component aligned within a first through hole cut out in the first level stack such that one of an upper or a lower surface of the first component is substantially flush with an respective upper or a lower surface of the first level stack second electrically conductive layer structures and/or second electrically insulating layer structures attached onto the upper and the lower surface of the first level stack thereby covering the first component at the upper and the lower surface of the first component and pressed to form a second level stack. A second component is aligned within a second through hole cut out in the second level stack such that one of upper or a lower surface of the second component is substantially flush with an upper or a lower surface of the second level stack.

An electronic apparatus includes a first circuit board, a stacked circuit that is provided on the first circuit board through first coupling terminals and has a structure in which arithmetic elements and memory elements are stacked through inter-element coupling terminals and to which a signal is inputted from the first circuit board, and a second circuit board that is provided on the stacked circuit through second coupling terminals and to which a result of processing is outputted from the stacked circuit, wherein a number of the first coupling terminals and a number of the second coupling terminals are smaller than that of the inter-element coupling terminals.

A substrate includes a first dielectric layer having a first surface and a second surface. The first dielectric layer includes a plurality of first conductive vias and a plurality of second conductive vias. These two kinds of conductive vias are formed to penetrate the first dielectric layer and have different orientations for reduce warpage of the substrate.

An electronic system is provided. The electronic system includes a base and a semiconductor device. The base having a device-attach region includes a build-up layer structure, a vertical interconnect structure and a first through via. The vertical interconnect structure and the first through via are formed passing through the build-up layer structure and located in the device-attach region. The vertical interconnect structure includes a buried via and a blind via electrically coupled to the buried via. The first through via is a straight through via. The semiconductor device is mounted on the device-attach region of the base.