A plated hole with a sidewall plating. The plated hole has a vent opening that has a sidewall of non-conductive material that is not plated. During attachment of a joint conductive material such as solder to the sidewall plating, gasses generated from the attachment process are outgassed through the vent opening.

A method for forming passive electrical devices that includes depositing a photo reactive layer over a sidewall of a via that extends through a printed circuit board; inserting a light pipe having a mask configured to provide a passive electronic device geometry within the via to an entire depth of the via; and exposing the photo reactive layer to radiation provided by the light pipe to provide a pattern having the passive electronic device geometry on the sidewall of the via.

Creating in-via routing with a light pipe is disclosed. A resist layer is applied over a layer of conductive material provided in a via. A light pipe is inserted into the via. The surface of the light pipe includes at least one masked portion and at least one unmasked portion. A portion of the resist layer is exposed with light emitted from the unmasked portions of the light pipe. Portions of the conductive layer corresponding to the exposed portion of the resist layer are then removed to create the in-via routing.

A circuit board includes a baseboard, a first conductive circuit layer, a second conductive circuit layer, at least one through hole, and a number of conductive lines. The first conductive circuit layer includes a number of first conductive circuit lines formed on a first side of the baseboard. The second conductive circuit layer includes a number of second conductive circuit lines formed on a second side of the baseboard. The through hole is defined through the first conductive circuit layer, the baseboard, and the second conductive circuit layer. The number of conductive lines are formed in an inner wall of the through hole and spaced apart around the through hole. Each conductive line electrically couples one of the first conductive circuit lines to a corresponding one of the second conductive circuit lines.

A multilayer printed circuit board is provided having a first conductive layer and a first plating resist selectively positioned within the first conductive layer. A second plating resist may be selectively positioned within a second conductive layer. A through hole extends through the first plating resist in the first conductive layer and the second plating resist in the second conductive layer. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

A method for making an interconnection component includes forming a mask layer that covers a first opening in a sheet-like element that includes a first opening extending between the first and second surfaces of the element. The element consists essentially of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. The first opening includes a central opening and a plurality of peripheral openings open to the central opening that extends in an axial direction of the central opening. A conductive seed layer can cover an interior surface of the first opening. The method further includes forming a first mask opening in at least a portion of the mask layer overlying the first opening to expose portions of the conductive seed layer within the peripheral openings; and forming electrical conductors on exposed portions of the conductive seed layer.

A printed wiring board includes a main substrate and a rising substrate. A support portion of the rising substrate is inserted into a slit in the main substrate. In a direction in which a plurality of first electrodes are aligned, a width of each of the plurality of first electrodes is larger than a width of each of a plurality of second electrodes, and the width of each of the plurality of second electrodes is arranged to fit within the width of each of the plurality of first electrodes.

A method for manufacturing an interconnect structure is provided. The method includes the following steps. An opening is through a substrate. A low-k dielectric block is formed in the opening. At least one first via is formed through the low-k dielectric block. A first conductor is formed in the first via.

The printed wiring board of the present disclosure includes: a plurality of insulating layers laminated in a thickness direction; a plurality of wiring conductors respectively correspondingly positioned between the plurality of insulating layers; a through hole penetrating the plurality of insulating layers and the plurality of wiring conductors in the thickness direction; and a through-hole conductor positioned on a wall surface of the through hole; each of the plurality of wiring conductors has a first surface facing the through hole, each of the plurality of insulating layers has a second surface facing the through hole, and the first surface is farther away from a central axis penetrating the through hole in the thickness direction than the second surface.

Provided is a substrate including a first wiring layer, wherein the first wiring layer has a structure in which among a plurality of first connection parts of a plurality of vias, at least one of first connection parts of two vias located closer to both ends of the first wiring layer is coupled to a body of the first wiring layer through a first conductive portion, each of the plurality of first connection parts being coupled to the first wiring layer, and a cross-sectional area of the first conductive portion is less than an area of a first part of the first wiring layer, the first part being in contact with a first connection part of a via other than the first connection parts of the two vias.