A board of a controller of a load drive device includes: wiring layers provided on front and rear surfaces and inside thereof and ground layers provided inside thereof. Each wiring layer is divided into: a first region in which a drive circuit is provided; and a second region in which a control circuit is provided. A first ground layer including a first ground pattern for a circuit which is electrically connected to a wiring pattern of each wiring layer is divided into: a third region which overlaps with the first region in a thickness direction, and in which the first ground pattern for a power system electrically connected to the drive circuit is provided, and a fourth region which overlaps with the second region in the thickness direction, and in which the first ground pattern for a control system electrically connected to the control circuit is provided.

Disclosed is an electronic apparatus including a substrate (20) and a connector (10) disposed on one edge constituting an outer periphery of the substrate (20). A slit (21) is formed in the substrate (20), with a starting point being a position between an end point on one side of the edge and the position where the connector (10) is disposed.

According to one or more embodiment, an electronic device includes a board. The board includes a first layer and a second layer. The first layer includes a first power supply pattern. The second layer includes a second power supply pattern. The second power supply pattern is electrically connected to the first power supply pattern. When viewed in a thickness direction of the board, half or more of the first power supply pattern overlaps the second power supply pattern, or at least a portion of the first power supply pattern overlaps a signal line provided in the second layer.

Printed circuit board (PCB), electrical structures including PCBs, and methods for making the same. One PCB structures includes: a substrate having a plurality of surfaces, including a first aerial main face (AMF), a second AMF, and a first peripheral end face (PEF), wherein the first PEF separates the first AMF from the second AMF, and a first plurality of contacts embedded in the first PEF, where each of the first plurality of contacts forms a contiguous contact with the first PEF and at least one of i) the second AMF, ii) the first AMF, and iii) another one of the plurality of surfaces.

According to one embodiment, a detection device includes a substrate, detection electrode, terminal formed of a metal material, lead, coating layer, conductive adhesion layer, and circuit board. The lead connects the electrode and the terminal. The coating layer covers the electrode and the lead, and partly covers the terminal. The adhesion layer covers a part of the terminal exposed from the coating layer and covers a part of the coating layer. The circuit board is connected to the terminal with the adhesion layer interposed therebetween. At least in an overlapping area where the adhesion layer covers the coating layer, an area of the metal material per unit area is smaller than that of the other area of the terminal.

In a suspension board, a ground layer and a first insulating layer are formed on a support substrate. The ground layer has electric conductivity higher than that of the support substrate. A power wiring trace is formed on the first insulating layer. A second insulating layer is formed on the support substrate to cover the ground layer and the first insulating layer. A write wiring trace is formed on the second insulating layer to at least partially overlap with the ground layer. A distance between the ground layer and the write wiring trace in a stacking direction of the support substrate, the first insulating layer and the second insulating layer is set larger than a distance between the power wiring trace and the write wiring trace in the stacking direction.

Disclosed is a printed circuit board (PCB) including a set of stacked metallization layers separated by a set of stacked electrical-insulating layers, respectively, wherein the set of stacked metallization layers includes top metallization layer, bottom metallization layer, and intermediate metallization layer; a via electrically coupled to the top metallization layer, the intermediate metallization layer, and the bottom metallization layer, wherein the top metallization layer, a portion of the via between the top metallization layer and the intermediate metallization layer, and the intermediate metallization layer are configured to route a data signal between a signal-in and a signal-out; and an electromagnetic absorbing material configured to reduce an intensity of a reflected signal resulting from the data signal propagating downward along a stub of the via and reflecting off the bottom metallization layer. The electromagnetic absorbing material may be attached to a bottom of the PCB and/or coaxially attached to the stub.

A land grid array (LGA) land pad having reduced capacitance is disclosed. The conductive portion of a land pad that overlaps a parallel ground plane within the substrate is reduced by one or more non-conductive voids though the thickness of the conductive portion of the land pad. The voids may allow the contact area of the land pad, as defined by the perimeter of the land pad, to remain the same while reducing the conductive portion that overlaps the parallel ground plane. Capacitance between the land pad and the parallel ground plane is reduced by an amount proportional to the reduction in overlapping conductive area.

An electronic device including: a discrete transistor including a semiconductor chip encapsulated in a package made of an insulating material leaving access to a first pad of connection to a first conduction terminal of the transistor; and a printed circuit board (320) including first (125) and second (129) separate connection pads, wherein the transistor is assembled on the printed circuit board so that the first connection pad (105) of the transistor is in contact with the first (125) and second (129) connection pads of the printed circuit board.

Systems and methods for providing a PWB. The methods comprise: forming a Core Substrate (CS) a First Via (FV) formed therethrough; disposing a First Trace (FT) on an exposed surface of CS that is in electrical contact with FV; laminating a first HDI substrate to CS such that FT electrically connects FV via with a Second Via (SV) formed through the first HDI substrate; disposing a Second Trace (ST) on an exposed surface of the first HDI substrate that is in electrical contact with SV; and laminating a second HDI substrate to the first HDI substrate such that ST electrically connects SV to a Third Via (TV) formed through the second HDI substrate. SV comprises a buried via with a central axis spatially offset from central axis of FV and SV. FV and SV have diameters which are smaller than TV's diameter.