Patent classifications
H05K2201/0969
WAVEGUIDE INTERFACE ARRANGEMENT
Provided is a waveguide interface arrangement for electrically connecting a waveguide device to a microwave conductor that runs in a metallization on one main side of a printed circuit board, PCB, comprising a PCB dielectric layer, a first PCB main side with a first PCB metallization and a first PCB aperture in the first PCB metallization, and a second PCB main side with a second PCB metallization and a second PCB aperture in the second PCB metallization. The first PCB aperture corresponds to a waveguide aperture and a backshort is attached to the second PCB main side, comprising a backshort dielectric layer, a first backshort main side with a first backshort metallization.
The second backshort metallization is electrically connected to the second PCB metallization.
The backshort aperture is adapted to face the second PCB aperture.
ELECTRONIC DEVICE
An electronic device is provided, including a substrate, a conductive element, and an insulating layer. The conductive element is disposed on the substrate. The conductive element includes a first layer, a second layer, and a third layer. The second layer is disposed on the first layer. The third layer is disposed on the second layer. The insulating layer is disposed on the conductive element. A thickness of the second layer is greater than a thickness of the first layer, and the thickness of the second layer is greater than a thickness of the third layer. There is a gap between the insulating layer and the conductive element.
ANTENNA INSTALLATION STRUCTURE AND ELECTRONIC DEVICE
An antenna installation structure includes an antenna substrate, an insulation layer, and a bonding material. The antenna substrate includes a dielectric base including first and second main surfaces, and an antenna conductor on the first main surface. The insulation layer is on the first main surface of the antenna substrate. The bonding material is between the insulation layer and a radiation side wall of a housing, is cured, and bonds the insulation layer to the radiation side wall. A linear expansion coefficient of the insulation layer is lower than a linear expansion coefficient of the bonding material and higher than a linear expansion coefficient of the antenna substrate.
ARRANGEMENT FOR HEAT EXCHANGE
An arrangement for exchanging heat between two bodies comprises a circuit board, having at least one first via and at least one second via, wherein at least one heat exchange structure is integrated in the circuit board, wherein the at least one heat exchange structure comprises two heat exchange layers and an intermediate layer arranged between the two heat exchange layers, wherein the two heat exchange layers are thermally joined to each other and electrically separated from each other by the intermediate layer, wherein a first heat exchange layer is associated with the first body and can be brought into thermal contact with it and a second heat exchange layer is associated with the second body and can be brought into thermal contact with it, wherein the at least one first via and the at least one second via are each led through the two heat exchange layers and the intermediate layer arranged between the two heat exchange layers, wherein the at least one first via is in contact only with the first heat exchange layer and is insulated from the second heat exchange layer, and wherein the at least one second via is in contact only with the second heat exchange layer and is insulated from the first heat exchange layer.
PRINTED CIRCUIT BOARD MESH ROUTING TO REDUCE SOLDER BALL JOINT FAILURE DURING REFLOW
Voids are introduced in a copper shape to reduce warpage experienced by a printed circuit board during a reflow process. Copper shapes on an outer layer of a printed circuit board may be used to connect large packages that include ball grid arrays to the printed circuit board. The copper shapes may induce warpage in the printed circuit board during the reflow process. Routing a mesh pattern of voids in the copper shapes may reduce solder ball joint cracking and pad cratering during reflow and make solder joints more reliable. The voids may make the copper shapes less ridged and change the copper heat dissipation profile to remove sharp warpage forces that cause solder joints to experience pad cratering. The voids may be 8 mil x 8 mil cuts or indentations in the copper shape.
Apparatus for shielding of surface-mount devices
An apparatus for a shielding structure for surface-mount components and filters to increase the signal isolation from input signal port to output signal port. An LTCC filter device with an increased rejection of undesired frequencies in a stopband and minimal distortion or loss of desired signals in a passband.
ELECTRONIC COMPONENT, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS
A manufacturing method of an electronic component includes preparing a first structure in which a first electrode is arranged on a first main surface of a first substrate, preparing a second structure in which a second electrode is arranged on a first main surface of a second substrate, and curing a bonding member while making the first main surface of the first substrate and the first main surface of the second substrate face each other via the bonding member and applying a force to the first structure and the second structure so as to pressurize the bonding member. At least one of the first electrode and the second electrode includes a window portion. In the curing, the bonding member is cured by irradiating the bonding member with light through the window portion.
Printed wiring line, electronic device, touch panel, gravure plate, printed wiring line formation method, touch panel production method, and electronic device production method
A printed wiring line formed on a substrate connects two different points on the substrate which are connectable by another printed wiring line with a shape of a straight-line segment and has a shape corresponding to at least one of: 1) a shape with no linear part parallel to the straight-line segment; 2) a shape with line segments connected in series, each line segment having a shape with no linear part parallel to the straight-line segment; 3) a shape having a part parallel to the straight-line segment and a part not parallel to the straight-line segment, length of the part parallel to the straight-line segment being not more than length of the straight-line segment; and 4) a shape in which line segments are connected in series, each line segment having a shape having a part parallel to the straight-line segment and a part not parallel to the straight-line segment.
Semiconductor device having buffer structure for external terminals
A semiconductor device, including a first board, a second board having a plurality of through holes passing therethrough, and a plurality of external terminals that are respectively press-fitted into the plurality of through holes of the second board, one end portion of each external terminal passing through the corresponding through hole and being fixed to a front surface of the first board. The second board is a printed circuit board that further includes, in a top view thereof, a plurality of support regions, each having one of the plurality of through holes formed therein, and a plurality of buffer regions respectively surrounding the plurality of support regions, each buffer region having at least one buffer hole and at least one torsion portion formed therein, the at least one torsion portion being connected to the support region surrounded by each buffer region.
METHOD AND APPARATUS FOR MOUNTING A DUT ON A TEST BOARD WITHOUT USE OF SOCKET OR SOLDER
A method is provided for mounting a semiconductor IC to a substrate without a socket or solder. The method includes disposing a guide structure on the substrate. The substrate has multiple contact pads disposed thereon. The substrate also has multiple nuts formed therein for connecting to one or more bolts. The method also includes placing the semiconductor IC inside the guide structure such that the semiconductor IC makes contact with the contact pads. A top plate is disposed on the semiconductor IC. Further, the top plate and the semiconductor IC are fastened to the substrate.