Provided is an FPC, including a first row of gold fingers and a second row of gold fingers disposed on a same layer, and multiple first connection lines. The first row of gold fingers includes multiple first gold fingers extending in a first direction and arranged in a second direction. The second row of gold fingers includes multiple second gold fingers extending in the first direction and arranged in the second direction. The multiple first connection lines are disposed in a different layer from the second row of gold fingers, electrically connected to the multiple first gold fingers, and insulated from the multiple second gold fingers and extend to an area where the second row of gold fingers is located. The first connection line includes a first wire and a second wire. The first wire includes a first portion, a second portion and a third portion connected in sequence.

Described herein are systems and methods for a design method and new interconnect structures with incorporated interdigital trapezoidal tabs structures enabled with materials with either larger permittivity or permeability for improved signal integrity.

A printed circuit board includes: an insulating layer; a first circuit pattern embedded in one surface of the insulating layer; and a second circuit pattern disposed on the one surface of the insulating layer and including a first metal layer and a second metal layer disposed on the first metal layer. An average width of the first metal layer is wider than an average width of the second metal layer.

A wiring board (10) includes a substrate (11) that is transparent, a wiring pattern region (20) disposed on the substrate (11) and having first-direction wiring lines (21), and a feeding unit (40) electrically connected to the first-direction wiring lines (21) of the wiring pattern region (20). Each first-direction wiring line (21) has a first region (26) positioned near the feeding unit (40) and a second region (27) that is a region other than the first region (26). A line width (W.sub.3) of the first-direction wiring line (21) in the first region (26) is larger than a line width (W.sub.1) of the first-direction wiring line (21) in the second region (27).

A printed wiring board includes a first resin insulating layer, a second resin insulating layer formed on a surface of the first layer, and a conductor layer formed on the surface of the first layer such that the second layer is covering the conductor layer and that the conductor layer includes first, second, third, fourth, fifth, and sixth circuits such that the third and fourth circuits are sandwiching the first circuit and that the fifth and sixth circuits are sandwiching the second circuit. Widths between the first and third circuits and between the first and fourth circuits are 5 μm to 14 μm, and when a width between the second and fifth circuits and a width between the second and sixth circuits is 20 μm or more, the upper surface of the first circuit, and the upper surface and side walls of the second circuit are formed to have unevenness.

Provided is a conductive pattern having at least one unit conductive pattern forming one touch pixel according to an aspect of the present invention. The at least one unit conductive pattern includes a plurality of nanostructures each having opposite ends. A ratio of nanostructures, both opposite ends of which are in contact with edges of the at least one unit conductive pattern to all nanostructures included in the at least one unit conductive pattern is 70% or more.

According to one embodiment, a detection device includes a substrate, detection electrode, terminal formed of a metal material, lead, coating layer, conductive adhesion layer, and circuit board. The lead connects the electrode and the terminal. The coating layer covers the electrode and the lead, and partly covers the terminal. The adhesion layer covers a part of the terminal exposed from the coating layer and covers a part of the coating layer. The circuit board is connected to the terminal with the adhesion layer interposed therebetween. At least in an overlapping area where the adhesion layer covers the coating layer, an area of the metal material per unit area is smaller than that of the other area of the terminal.

According to one aspect of the present disclosure, a printed circuit board includes: an insulating base film; and a plurality of wiring portions formed on a surface of the base film, wherein the wiring portions include a seed layer that is directly or indirectly layered on the surface of the base film and a metal layer that is layered on the seed layer, wherein the base film has a wiring area including the plurality of wiring portions and a non-wiring area not including the wiring portions, wherein the plurality of wiring portions include at least one outermost boundary wiring portion and a plurality of inner wiring portions other than the outermost boundary wiring portion, wherein the outermost boundary wiring portion is formed on an outermost side of the base film in the wiring area and at a boundary between the wiring area and the non-wiring area, wherein an average width of the outermost boundary wiring portion is 30 μm or more, wherein an average width of the inner wiring portions is 20 μm or less, and wherein an average aspect ratio of the inner wiring portions is 1.5 or more.

In this circuit board 30, first signal wiring portions 351 and second ground wiring portions 353 of a first wiring layer 34 are adjacent to each other in a pitch direction. Further, second signal wiring portions 381 and first ground wiring portions 383 of a second wiring layer 37 are adjacent to each other in the pitch direction. In the pitch direction, outer edges 405 of line portions 345 of two first signal wiring portions 351 are located more inward than both edges 435 of a line portion 375 of the first ground wiring portions 383. Outer edges 415 of line portions 375 of two second wiring portions 381 are located more inward than both edges 425 of the line portion 345 of the second ground wiring portion 353. This achieves good signal transmission characteristics without providing a ground layer separate from a signal layer.

Described herein are systems and methods for a design method and new interconnect structures with incorporated interdigital trapezoidal tabs structures enabled with materials with either larger permittivity or permeability for improved signal integrity.