An electronic device is disclosed and includes a base substrate, a circuit layer, and a plurality of light-emitting elements. The base substrate has a plurality of through holes, the circuit layer is disposed on the base substrate, and the light-emitting elements are disposed on the first circuit layer. An absolute value of a difference between two adjacent spacings of the plurality of through holes of the base substrate is less than 0.5 times radius of curvature of the electronic device when the electronic device is bent.

An electronic device is disclosed and includes a substrate, a circuit layer, and a plurality of diodes. The substrate has a plurality of structures. The circuit layer is disposed on the substrate. The diodes are disposed on the circuit layer, wherein a first spacing is defined as a distance between a center point of a first one of the structures and a center point of a second one of the structures, a second spacing is defined as a distance between a center point of a third one of the structures and a center point of a fourth one of the structures, and an absolute value of a difference between the first spacing and the second spacing is less than 0.5 times radius of curvature of the electronic device when the electronic device is bent.

A light sensing module and a display apparatus are provided. The light sensing module includes a circuit board and a light sensing device, wherein the circuit board includes a mounting region and a device region surrounding the mounting region, an encapsulation layer is disposed on the device region, and a light sensing device, a light sensing hole and a barrier structure are provided on the mounting region, a vertical projection of the light sensing device on the mounting region at least partially overlaps with a vertical projection of the light sensing hole on the mounting region, and the barrier structure is disposed around the periphery of the light sensing hole, and separates the encapsulation layer from the light sensing hole.

A light sensing module and a display apparatus are provided. The light sensing module includes a circuit board and a light sensing device, wherein the circuit board includes a mounting region and a device region surrounding the mounting region, an encapsulation layer is disposed on the device region, and a light sensing device, a light sensing hole and a barrier structure are provided on the mounting region, a vertical projection of the light sensing device on the mounting region at least partially overlaps with a vertical projection of the light sensing hole on the mounting region, and the barrier structure is disposed around the periphery of the light sensing hole, and separates the encapsulation layer from the light sensing hole.

A component carrier having a base structure consisting of an electrically conductive material, an electronic component arranged on the base structure and a surrounding structure on the base structure, where the surrounding structure at least partially surrounds the electronic component laterally.

A chip electronic component includes a stack, a first external electrode disposed at least on a first end surface and a first main surface of the stack, a second external electrode disposed at least on a second end surface and a first main surface of the stack, a first bump disposed at least on a portion of the first external electrode on the first main surface, and a second bump disposed at least on a portion of the second external electrode on the first main surface. The first bump and the second bump each have a porosity greater than or equal to about 5% and less than or equal to about 40%.

A board having an electronic component mounted thereon includes a capacitor body; a pair of external electrodes disposed on both ends of the capacitor body, respectively; a pair of metal frames including a pair of connection portions connected to the pair of external electrodes, respectively, and a pair of mounting portions each having a protrusion on a lower side thereof, respectively; a board; and a pair of electrode pads disposed on an upper surface of the board and connected to the pair of metal frames, respectively, and each having a groove portion corresponding to the protrusion on an upper surface thereof.

A circuit board includes a substrate, a plurality of contacts disposed on a surface of the substrate, and a solder mask. The contacts have a plurality of plating regions and a metal layer on the plating regions, and the plating regions have at least two different sizes. The solder mask covers the surface of the substrate and covers edges of the plating regions, in which topmost surfaces of the contacts are below a top surface of the solder mask, and a gap between the topmost surfaces of the contacts and the top surface of the solder mask is larger than 0 μm and is smaller than 5 μm.

A multilayer wiring board that improves the reliability of connection at a via hole connection portion, and a method for producing the multilayer wiring board. In a multilayer wiring board comprising a plurality of metal wiring layers alternately laminated with insulating layers interposed therebetween are electrically connected to each other via a via hole plated layer, wherein a dissimilar metallic layer, made from material different from that of the metal wiring layers, is interposed between each of the metal wiring layers on the bottom surface of the via hole and the via hole plated layer, and the dissimilar metallic layer interposed between the each of the metal wiring layers on the bottom surface of the via hole and the via hole plated layer is arranged in a concave shape on the surface of the concave portion formed in the metal wiring layer on the bottom surface of the via hole.

A method of fabricating a circuit board includes forming a conductive layer on a surface of a substrate, and patterning the conductive layer to define a plurality of plating regions and a plurality of plating lines. The plating regions have at least two different sizes, a first group of the plating regions are interconnected by a first plating line of the plating lines, and a second group of the plating regions are interconnected by a second plating line of the plating lines. A ratio of a total area of the first group of the plating regions to a total area of the second group of the plating regions is from about 1 to about 5. A solder mask is formed on the surface of the substrate to cover the plating lines and partially expose the plating regions. At least one metal layer is electroplated on the exposed plating regions.