A method of fabricating a circuit board includes forming a conductive layer on a surface of a substrate, and patterning the conductive layer to define a plurality of plating regions and a plurality of plating lines. The plating regions have at least two different sizes, a first group of the plating regions are interconnected by a first plating line of the plating lines, and a second group of the plating regions are interconnected by a second plating line of the plating lines. A ratio of a total area of the first group of the plating regions to a total area of the second group of the plating regions is from about 1 to about 5. A solder mask is formed on the surface of the substrate to cover the plating lines and partially expose the plating regions. At least one metal layer is electroplated on the exposed plating regions.

A board having an electronic component mounted thereon includes a capacitor body; a pair of external electrodes disposed on both ends of the capacitor body, respectively; a pair of metal frames including a pair of connection portions connected to the pair of external electrodes, respectively, and a pair of mounting portions each having a protrusion on a lower side thereof, respectively; a board; and a pair of electrode pads disposed on an upper surface of the board and connected to the pair of metal frames, respectively, and each having a groove portion corresponding to the protrusion on an upper surface thereof.

A component carrier with a first component carrier structure including a first stack which has at least one first electrically conductive layer structure and at least one first electrically insulating layer structure is disclosed. The at least one first electrically conductive layer structure has a first contact element which extends up to a first contact surface of the first stack. An electrically conductive connection medium is directly connected to the first contact element at the first contact surface by filling at least one recess of the first contact element. The at least one recess having a larger dimensioned cavity delimited by a smaller dimensioned surface profile.

According to one embodiment, a semiconductor device comprises a circuit board and a semiconductor package mounted on the circuit board. The semiconductor package comprises a semiconductor chip, a first connector on a bottom surface of the semiconductor package and electrically connected to the semiconductor chip, and a metal bump coupled to the first connector and electrically connected to a second connector on the circuit board. The first connector has a contact surface facing the second connector. The contact surface has a recessed portion into which the metal bump extends.

A control device for an electric machine includes a circuit board and a cooling body, which are joined together, wherein a heat-conducting paste is introduced between the circuit board and the cooling body at least for thermally connecting the circuit board to the cooling body. The circuit board and/or the cooling body has at least one recess, wherein the recess is formed in the lateral direction between a region to be protected and the introduced heat-conducting paste in such a way that, when the circuit board and the cooling body are joined, an excess portion of the laterally spreading heat-conducting paste can be received by the recess.

A metal-ceramic substrate (1) comprising an insulating layer (11) extending along a main extension plane (HSE) and comprising a ceramic, and a metallisation layer (12) bonded to the insulating layer (11) over a bonding area (A), the bonding area (A) being delimited by at least one edge (K) in a plane parallel to the main extension plane (HSE), characterized in that the edge (K) is at least partially covered with a filling material (2) and an edge region (RB) of the metallisation layer (12) adjoining the edge has a material weakening.

A bulb-type light source includes a globe transmitting a light and at least one light emitting device filament disposed in the globe. The light emitting device filament includes a substrate including n (n is a natural number equal to or greater than 2) flat portions and n−1 bendable portions disposed between the flat portions, a plurality of light emitting device chips disposed on the flat portions, a fluorescent substance layer covering each light emitting device chip and converting a wavelength of a light from each light emitting device chip, and a connection line disposed on the flat portions and electrically connecting the light emitting device chips adjacent to each other between the adjacent light emitting device chips.

An electronic assembly includes a printed wiring board (PWB), and a stiffener secured to the PWB. The stiffener includes one or more tray sections. One or more electronic modules is secured respectively to the one or more tray sections of the stiffener.

A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.

A method for manufacturing a printed wiring board includes forming a base insulating layer, forming a conductor layer on the base layer, forming a solder resist layer on the base layer such that the resist layer covers the conductor layer, forming first opening exposing a first pad of the conductor layer, forming second opening exposing a second pad of the conductor layer and having diameter smaller than diameter of the first opening, forming a first bump on the first pad, and forming a second bump on the second pad such that the second bump has diameter smaller than diameter of the first bump. The first bump includes a first base plating layer and a first top plating layer, and the second bump includes a second base plating layer and a second top plating layer having upper surface higher than the uppermost position of upper surface of the first top layer.