Patent classifications
H05K2201/098
Chip interconnect devices
An interconnect device may include a first center conductor of a first material that has a first durometer. The first center conductor may be surrounded by a first inner dielectric ring, which may be surrounded by a conductive region of a second material having a second durometer. The second durometer may be different from the first durometer. The conductive region may have a first end that defines a first plane and a second end that defines a second plane. An outer dielectric ring may surround the conductive region. The first center conductor may have a first bulb and a second bulb, the first bulb may extend in a direction away from the second plane and beyond the first plane, and the second bulb may extend in a direction away from the first plane and beyond the second plane.
Component carrier with adhesion promoting shape of wiring structure
A component carrier includes a base structure and an electrically conductive wiring structure on the base structure. The wiring structure has a nonrectangular cross-sectional shape configured so that an adhesion promoting constriction is formed by at least one of the group consisting of the wiring structure and a transition between the base structure and the wiring structure.
RESIN MULTILAYER BOARD
A resin multilayer board includes an insulating substrate including a first main surface and mounting electrodes only on the first main surface. The insulating substrate includes first and second resin layers that are laminated. The Young's modulus of the second resin layers is higher than that of the first resin layers. The first and second resin layers are arranged in a distributed manner along a lamination direction of the first and second resin layers. The insulating substrate includes a first and second portions that are two equally divided portions of the insulating substrate in the lamination direction and are respectively positioned closer to the first main surface and farther from the first main surface, and a volume ratio of the second resin layers in the first portion is higher than a volume ratio of the second resin layers in the second portion.
High power RF capacitor
A high power radiofrequency (RF) capacitor, integrated circuit board/capacitor and methods for manufacture therefor can include a dielectric substrate, and a first metallic layer and a second metallic layer that can be deposited on opposite sides of the dielectric substrate, and a ground plane that can be co-planar with one of the metallic layers. This can establish a broadside coupling capacitance effect between the first metallic layer and the second metallic layer. The first metallic layer and the second metallic layer can have a circular profile when viewed in plan view; alternatively, the first metallic layer and second metallic layer can have a T-shaped profile when viewed in plan view. The desired profile and the desired profile geometry can depend on the design power and operating frequency for the capacitor can depend on whether the capacitor must operate as a series capacitor or a shunt capacitor.
PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a printed circuit board includes providing an insulating layer, forming a plating seed layer on the insulating layer, forming a first circuit pattern on the plating seed layer and a second circuit pattern on the first circuit pattern, and forming a top metal layer on the second circuit pattern. The second circuit pattern can be thinner than the first circuit pattern, and the top metal layer can be wider than the second circuit pattern.
Printed circuit board and method of fabricating the same
A printed circuit board includes an insulating layer, a circuit pattern on the insulating layer, and a surface treatment layer on the circuit pattern. The surface treatment layer includes a bottom surface having a width wider than a width of a top surface of the circuit pattern.
Wiring board, electronic device, and electronic module
A wiring board includes an insulating substrate including a cutout portion that opens in a main surface of the insulating substrate and a side surface of the insulating substrate, an inner surface electrode on an inner surface of the cutout portion, an external electrode on the main surface of the insulating substrate, and a connecting section where the inner surface electrode and the external electrode are connected to each other. The connecting section is thicker than the inner surface electrode and the external electrode.
Electronic Shielding of Antennas from Fan Controls in a Compact Electronic Device
A compact electronic device for wireless communication is disclosed. The compact electronic device includes a main printed circuit board, one or more antennas, at least one conductor, and a shell. The one or more antennas are configured for wireless communication. The at least one conductor being configured to provide at least one of control signals and power to a fan. The shell mounts the fan relative to the main printed circuit board. The shell includes walls forming a cavity. The walls encapsulate the conductor in the cavity.
WIRING SUBSTRATE DEVICE
A wiring substrate device includes a wiring substrate, a plurality of terminals each of which is provided upright on the wiring substrate and has a lower end, an upper end and a narrowed part between the lower end and the upper end, and a plurality of solders each of which has a melting point lower than the terminals and covers a surface of the corresponding terminal.
PRINTED CIRCUIT BOARD, OPTICAL MODULE, AND OPTICAL TRANSMISSION EQUIPMENT
Provided is a printed circuit board realizing selective inhibition of electromagnetic noise and enabling high-density arrangement of differential transmission lines without increasing cost. The printed circuit board includes a pair of strip conductors (first layer), a first resonance conductor plate, a ground conductive layer (together with a second layer) including an opening portion, a second resonance conductor plate (third layer), a third resonance conductor plate (fourth layer), first via holes connecting the first and second resonance conductor plates, a second via hole connecting the second and third resonance conductor plates, and third via holes connecting the third resonance conductor plate and the ground conductive layer, wherein a polygon obtained by sequentially connecting centers of the adjacent third via holes overlaps so as to include the first resonance conductor plate, and center-to-center distance between the adjacent third via holes is 0.5 wavelength or less at frequency corresponding to the bit rate.