Patent classifications
H05K2201/10454
ELECTRONIC PACKAGE MODULE AND METHOD FOR FABRICATION OF THE SAME
An electronic package module and a method for fabrication of the same are provided. The electronic package module has the circuit substrate with the flat surface and the electronic component located on the circuit substrate. The electronic component includes the input end located on the flat surface of the circuit substrate and electrically connected to the circuit substrate. The electronic component includes the main part located on the input end and the ground end located on the main part. The input end and the ground end are located on two opposite sides of the main part separately and are located between the ground end and the circuit substrate. The input end, the main part and the ground end are arranged along the normal direction of the flat surface.
Small footprint semiconductor package
A semiconductor assembly includes a substrate with electrically conductive regions and a semiconductor package. The semiconductor package includes a semiconductor die, first and second terminals, and a mold compound. The die has opposing first and second main surfaces, an edge disposed perpendicular to the first and second main surfaces, a first electrode at the first main surface, and a second electrode at the second main surface. The first terminal is attached to the first electrode. The second terminal is attached to the second electrode. The mold compound encloses at least part of the die and the first and second terminals so that each of the terminals has a side parallel with and facing away from the die that remains at least partly uncovered by the mold compound. The first and second terminals of the semiconductor package are connected to different ones of the electrically conductive regions of the substrate.
Systems and methods for inter-chip communication
A quilt packaging system includes a first and second electronic device each comprising a plurality of edge surfaces at least a first edge surface of which comprises one or more interconnect modules disposed thereon. The first edge surface of the second electronic device is positioned contiguous to the first edge surface of the first electronic device, and at least one of the one or more interconnect nodules disposed on the first edge surface of the first electronic device is configured to be in physical contact with at least one of the one or more interconnect nodules disposed on the first edge surface of second electronic device so as to provide an electrical connection between the first and second electronic devices at the first edge surfaces of the first and second electronic device.
PLANAR ILLUMINATION DEVICE
A planar illumination device according to an embodiment includes a light source, a circuit board and a pair of routing portions. The light source has a light emitting surface that emits light. The light source is mounted on the circuit board. A pair of land portions is provided on the circuit board, serves as a region where solder for electrically connecting respectively a pair of electrodes of the light source thereto is applied, is formed of an electrically conductive material, and corresponds to the electrodes. The pair of routing portions extends from each of the pair of land portions to at least a cover lay that protects a wiring on the circuit board and is formed of an electrically conductive material integrated with the land portions. First missing portions, being a region where the electrically conductive material is missing, are provided in each of the pair of routing portions.
Electronic device
An electronic device includes a substrate having a first surface and a second surface in a front-back relation, a first electronic component mounted on the second surface, and a lead joined to the second surface of the substrate via a conductive joint member, wherein the lead includes a base end portion extending in a direction along the substrate and joined to the second surface via the joint member, a distal end portion located distally from the substrate with respect to the base end portion in a thickness direction of the substrate and having a terminal surface, and a coupling portion coupling the base end portion and the distal end portion, and 1>2, wherein, as seen from a direction orthogonal to a plane along which the lead extends, an angle formed by a line connecting an outermost position in which the joint member contacts the base end portion and an outer edge of the substrate and the base end portion is 1, a distance between the first electronic component and the terminal surface in the thickness direction of the substrate is d1, a distance between a boundary part between the base end portion and the coupling portion and the joint member in the direction along the substrate is d2, and arctan(d1/d2)=2.
PACKAGED ELECTRICAL DEVICES AND RELATED METHODS
In some embodiments, a packaged device can include an electrical device having first and second electrodes implemented on opposite sides of a body. The electrical device can be sandwiched between first and second terminal assemblies, with the first and second terminal assemblies being configured to provide the packaged device with a surface mount device (SMD) format, thereby allowing the electrical device to be easily mounted on a surface of a circuit board.
High Speed Network Switch With Orthogonal Pluggable Optics Modules
The present disclosure describes a network switch design that includes a vertical switch circuit board that is mounted parallel to the front panel of the network switch. The vertical circuit board supports switch chip(s) to process and forward packets and pluggable module connectors to receive pluggable optics modules that provide connections to other network switches. The pluggable module connectors are horizontally oriented to facilitate routing of electrical signal traces. The arrangement of the circuit board, switch chip(s) and pluggable module connectors achieves reduced lengths for the electrical signal traces that connect the switch chip(s) to the pluggable module connectors. The design improves cooling by providing separate airflow regions between the switch chip heatsink(s) and the optics modules.