A package structure includes a metal layer, a composite layer of a non-conductor inorganic material and an organic material, a sealant, a chip, a circuit layer structure, and an insulating protective layer. The composite layer of the non-conductor inorganic material and the organic material is disposed on the metal layer. The sealant is bonded on the composite layer of the non-conductor inorganic material and the organic material. The chip is embedded in the sealant, and the chip has electrode pads. The circuit layer structure is formed on the sealant and the chip. The circuit layer structure includes at least one dielectric layer and at least one circuit layer. The dielectric layer has conductive blind holes. The insulating protective layer is formed on the circuit layer structure. The insulating protective layer has openings, so as to expose parts of the surface of the circuit layer structure in the openings.

The present disclosure relates to the field of fabricating microelectronic packages, wherein magnetic particles distributed within a solder paste may be used to form a magnetic intermetallic compound interconnect. The intermetallic compound interconnect may be exposed to a magnetic field, which can heat a solder material to a reflow temperature for attachment of microelectronic components comprising the microelectronic packages.

An electrical connector used for connecting an chip module to a printed circuit board includes an insulating housing, a number of terminals and a cover. The insulating housing includes a body portion. The terminals are insert molded in the body portion. The body portion includes an upper face and a lower face. Each of the terminals includes a first soldering portion extending upwardly beyond the upper face and a second soldering portion extending downwardly beyond the lower face. The cover covers the insulating housing. The electrical connector has a simple structure and a simple manufacturing process.

An embedded printed circuit board includes a first substrate, a semiconductor chip mounted on the first substrate, a second substrate provided on the first substrate via the semiconductor chip so that the semiconductor chip is sandwiched between the first substrate and the second substrate, a first resin filled between the semiconductor chip and the first substrate and having a cladding portion covering a side surface of the semiconductor chip, and a second resin filled between the first substrate and the second substrate and encapsulating the semiconductor chip and the first resin. The first resin includes a protrusion protruding from the cladding portion toward the second substrate.

Various implementations disclosed herein include arrangements that reduce parasitic inductance associated with a discrete decoupling capacitor by using a three-terminal capacitor and a staggered array of power supply and ground connections. In some implementations, a capacitive decoupling arrangement includes a substrate, an array of electrical vias of first and second types, and a capacitive arrangement on one side of the substrate coupled to the array of electrical vias. The array of electrical vias includes a first type of vias and a second type of vias. The capacitive arrangement is coupled between two respective vias of the first type of vias and two respective vias of the second type of vias on the first planar surface of the substrate. The capacitive arrangement includes a plurality of capacitive elements electrically arranged in parallel between the two respective vias of the first type of vias and the two respective vias of the second type of vias.

A wiring board includes a first insulating layer made of a single layer of non-photosensitive resin including a reinforcing member, a center position of the reinforcing member being positioned on a side toward a first surface with respect to a center of the first insulating layer in a thickness direction; a layered structure of a wiring layer and an insulating layer, stacked on the first surface of the first insulating layer; a through wiring provided to penetrate the first insulating layer, the through wiring and the first insulating layer forming a first concave portion at a second surface of the first insulating layer, in which the second end surface of the through wiring is exposed; and a pad for external connection formed at the second surface of the first insulating layer at a position corresponding to the through wiring and having a second concave portion.

A method of manufacturing package structure with following steps is disclosed herein. An insulating composite layer is formed on a metal layer of a carrier board. A chip packaging module including a sealant and a first chip embedded therein is disposed on the insulating composite layer, in which the first chip has a plurality of conductive pads. A first circuit layer module including a dielectric layer and a circuit layer is formed on the chip packaging module, in which the circuit layer is on the dielectric layer and electrically connected to the conductive pads through a conductive vias in the dielectric layer. A second chip is disposed on the first circuit layer module. A second circuit layer module is formed on the first circuit layer module and the second chip. A protecting layer is formed on the second circuit layer module.

A system on package SoP module includes a printed circuit board (PCB) having a first side and an opposing second side, a first IC attached to the first side, a second IC attached to the second side. The PCB also provides electrical paths for connecting the first IC and the second IC. Conductors by which the second IC is attached to the PCB also allow for electrical testing of the first IC when the SoP is in a system level state.

Embodiments are related to fluidic assembly and, more particularly, to systems and methods for forming physical structures on a substrate.

A package component includes a dielectric layer and a metal pad over the dielectric layer. A plurality of openings is disposed in the metal pad. The first plurality of openings is separated from each other by portions of the metal pad, with the portions of the metal pad interconnected to form a continuous metal region.