A ball grid array device includes a monitoring circuit of inactive solder joints and a processor such as a field programmable gate array (FPGA) or other processor capable of determining the open or closed status of the monitoring circuit. The monitoring circuit traverses one or more of the solder joints between components being joined, such as a printed circuit board and an integrated circuit device. In certain embodiments, the inactive solder joints may be located within regions of the ball grid array that are predisposed to failure, such as at the periphery or corners of the printed circuit board, or proximate to regions that experience a broad range of operating temperatures. The failure of a solder joint within the monitoring circuit can be used to schedule maintenance of the ball grid array device prior to failure of an active solder joint.

An integrated-circuit package includes a flexible electrical-connection element sandwiched between a first face of a first multilayer support substrate and a second face of a second multilayer support substrate. The flexible electrical-connection element laterally projects with respect to, and is in electrical contact with at least one of, the multilayer support substrates. The flexible electrical-connection element and the first multilayer support substrate include, at a first region, respectively two first mutually facing orifices defining together a first cavity. The first cavity is at least partially closed off by a first part of the second face of the second multilayer support substrate. A first component is located in the first cavity, attached at the first part of the second face of the second multilayer support substrate and in electrical contact with the flexible electrical-connection element through the second multilayer support substrate.

A component carrier includes a base structure and an electrically conductive wiring structure on the base structure. The wiring structure has a nonrectangular cross-sectional shape configured so that an adhesion promoting constriction is formed by at least one of the group consisting of the wiring structure and a transition between the base structure and the wiring structure.

An integrated circuit includes a main body having a top and a bottom; and upper pins placed on the top of the main body, and lower pins placed on the bottom of the main body, in which each of the upper pins has a first protruding portion protruding toward outside from a side or the top of the main body, and each of the lower pins has a second protruding portion protruding toward outside from the side or the bottom of the main body.

An electronic control unit includes: a wiring substrate having a first surface on which a conductor wire is formed; a first electronic component that is implemented on the first surface of the wiring substrate, and has a large heat generation amount; a second electronic component that is implemented on the first surface of the wiring substrate, and has a heat generation amount smaller than the first electronic component; and a resin that covers the first electronic component, the second electronic component, and the first surface of the wiring substrate, and a second surface of the wiring substrate that is opposite to the first surface. A distance between an outer surface of the resin immediately below the first electronic component, and the second surface of the wiring substrate is longer than a distance between an outer surface of the resin immediately above the second electronic component, and the first surface of the wiring substrate.

Systems, apparatuses, and methods for routing and transmitting signals in an electronic device are described. Various signal paths may be routed to avoid or limit reference transitions or transitions between layers of a structure of a device (e.g., printed circuit board (PCB)). In a memory module, for example, different data inputs/outputs (e.g., DQs) may be routed through different layers of a PCB according to their relative location to one another. For instance, DQs associated with even bits of a byte may be routed on one layer of a PCB near one ground plane, and DQs associated with odd bits of the byte may be routed on a different layer of the PCB near another ground plane. Each of the DQs may be subject to a single reference layer change, which may occur at or near a DRAM of a memory module (e.g., in the DRAM ball grid array (BGA) area).

A semiconductor device includes a substrate comprising an antenna and a conductive feature; an integrated circuit (IC) die attached to the substrate and comprising a radio frequency (RF) circuit; and a flexible circuit integrated with the substrate, where the flexible circuit is electrically coupled to the IC die and the substrate, a first portion of the flexible circuit being disposed between opposing sidewalls of the substrate, a second portion of the flexible circuit extending beyond the opposing sidewalls of the substrate, the second portion of the flexible circuit comprising an electrical connector at a distal end.

Provided is a method of manufacturing a printed circuit board having test points in which test points and pads are formed on the printed circuit board and then are electrically connected to each other, so that it is possible to form the pads having a pitch interval smaller than that in the related art. This may contribute to miniaturization of the printed circuit board by mounting a connector smaller than that in the related art on the printed circuit board, and may enable the preformed test points to be used as they are even after the connector used is removed from the printed circuit board. Also provided is a printed circuit board manufactured thereby.

A timing control (TCON) board and a display device are provided. The TCON board includes a TCON chip and a CB. A plurality of heat dissipating terminals are provided to commonly connect the TCON chip to the CB, increasing a total contact area of the TCON board and the CB. Therefore, heat dissipation efficiency of the TCON chip is improved. At the same time, the heat dissipating terminals greatly reduce a pseudo connection percentage. Hence, heat dissipation performance and electrical performance of the entire TCON chip are avoided to be impacted.

A current sensor system includes a current sensor integrated circuit (IC) and a printed circuit board (PCB) having a ground plane with a feature configured to reduce an eddy current. The current sensor IC includes a lead frame comprising a die attach pad and at least one lead, a semiconductor die having a first surface attached to the die attach pad and a second, opposing surface, at least one magnetic field sensing element supported by the semiconductor die and configured to sense a current in a proximate primary conductor, and a non-conductive mold material enclosing the semiconductor die and a portion of the at least one lead. The PCB ground plane feature can take various forms such as a hole of a dimension larger than the current sensor IC, elongated cuts, or x-shaped cuts.