A manufacturing method for a circuit board in which a pin inserted in a through-hole of a land is welded to the land is disclosed. The land is covered with a white layer, and an irradiation angle of a laser beam with respect to the circuit board is adjusted so that reflected light of the laser beam emitted to the pin reaches the white layer on the land. As the reflected light of the laser beam is allowed to reach a white region provided on the land, the reflected light is scattered on the white region. A rate of absorption of the laser beam by the land is decreased, and a temperature increase of the land is restrained. As a result, a damage of an insulating part around the land is restrained.

Systems and methods for providing a PWB. The methods comprise: forming a Core Substrate (CS) a First Via (FV) formed therethrough; disposing a First Trace (FT) on an exposed surface of CS that is in electrical contact with FV; laminating a first HDI substrate to CS such that FT electrically connects FV via with a Second Via (SV) formed through the first HDI substrate; disposing a Second Trace (ST) on an exposed surface of the first HDI substrate that is in electrical contact with SV; and laminating a second HDI substrate to the first HDI substrate such that ST electrically connects SV to a Third Via (TV) formed through the second HDI substrate. SV comprises a buried via with a central axis spatially offset from central axis of FV and SV. FV and SV have diameters which are smaller than TV's diameter.

A probe card device includes a probe head including a plurality of pins, wherein each of the pins includes a body, a first metal layer formed on the body, and a second metal layer covering the first metal layer; a multi-layered flexible board electrically connected to the pins; a support plate, the multi-layered flexible board disposed on a first surface of the support plate; and a circuit board electrically connected to the multi-layered flexible board.

An interposer and method of providing spatial and arrangement transformation are described. An electronic system has an electronic package, a motherboard and an interposer between the package and the motherboard. The interposer has signal and ground contacts on opposing surfaces that are respectively connected. The contacts opposing the package has a higher signal to ground contact ratio than the contacts opposing the motherboard, as well as different arrangements. Ground shielding vias in the interposer, which are connected to a ground plane, electrically isolate the signals through the interposer. The package may be mounted on a shielded socket such that signal and ground pins are mounted respectively in signal and ground socket mountings, ground shielding vias are between the signal socket mountings, and the ground socket mountings contain plated socket housings.

The present invention provides a package substrate in which metal pins capable of providing an electrical connection are disposed without tilting, and a method of producing the package substrate. The present invention provides a package substrate including: a substrate; and an electrode disposed on a surface of the substrate, wherein a metal pin is disposed on the electrode via a cured product of a conductive paste containing a metal powder and a thermosetting resin, and the metal powder contains a low-melting point metal and a high-melting point metal having a melting point higher than that of the low-melting point metal.

Pin layouts for HSIO require a large number of pins due to isolation requirements. Differential signaling can be used in high speed transmission and reception. A single lane for operation at 6 to 8 Gbps speed typically a total of six to eight pins. At higher speeds, conventional technique to meet isolation requirements is to increase the number of ground pins per lane. With many lanes, the number of pins can become cumbersome. To address such issues, it is proposed to provide pin patterns that leverage differential cancellation to enhance signal isolation so that operation speed can increase while also reducing the number of pins so that the number of pins of a package is less cumbersome.

Systems and methods for providing a PWB. The methods comprise: forming a Core Substrate (CS) a First Via (FV) formed therethrough; disposing a First Trace (FT) on an exposed surface of CS that is in electrical contact with FV; laminating a first HDI substrate to CS such that FT electrically connects FV via with a Second Via (SV) formed through the first HDI substrate; disposing a Second Trace (ST) on an exposed surface of the first HDI substrate that is in electrical contact with SV; and laminating a second HDI substrate to the first HDI substrate such that ST electrically connects SV to a Third Via (TV) formed through the second HDI substrate. SV comprises a buried via with a central axis spatially offset from central axis of FV and SV. FV and SV have diameters which are smaller than TV's diameter.

An electronic assembly includes an electronic package having an integrated circuit component and interposer assemblies with compressible interposer contacts electrically connected thereto. Cable connector modules are coupled to the interposer assemblies. A cover assembly is coupled to the upper surface of the electronic package over the cable connector modules. The cover assembly includes bridge assemblies having plates in a plate stack that are independently movable. A load plate engages upper edges of the plates of the bridge assemblies and press against the plates to drive the bridge assemblies into the cable connector modules using compression hardware. The cable connector modules compress the interposer contacts of the interposer assemblies when the load plate presses the plates of the bridge assemblies into the cable connector modules.

Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.

A printed circuit board (PCB) system includes an integrated circuit (IC) package having a main IC chip that is electrically coupled to a top surface of a package substrate. A first printed circuit board (PCB) is electrically coupled to first contact structures on a bottom surface of the package substrate. A heat dissipation member is coupled to the main IC chip. A memory module is configured to electrically couple, via an interposer, with second contact structures on a top surface of the package substrate while the heat dissipation member dissipates heat from the main IC chip away from one or more memory IC chips on the memory module. The interposer is configured to electrically couple the second contact structures of the IC package with the memory module while the heat dissipation member dissipates heat from the main IC chip away from the one or more memory IC chips.