A method of manufacturing a component carrier is disclosed. The method includes galvanically depositing at least part of at least one electrically conductive pillar on a component, and inserting the at least one electrically conductive pillar and an electrically insulating layer structure into one another.

A control circuit board includes first and second elements on each surface of a board member. The first and the second elements respectively have first and third edge portions, which are opposite to each other and second and fourth edge portions which are opposite to each other. A plurality of signal input pins are provided to the first edge portion, a plurality of signal output pins are provided to the third edge portion, a plurality of between-element communication input pins are provided to the second edge portion, and a plurality of between-element communication output pins are provided to the fourth edge portion, respectively. A common signal is input to the first and second elements and a communication is performed between the first element and the second element. Loss of control function can be surely prevented while suppressing enlargement of the board and increase of development/production cost.

An information handling system (IHS) has a circuit board assembly with a dual-sided interposer substrate that is inserted between a baseboard and a processor integrated circuit having a second pattern of electrical contacts. The dual interposer substrate formed of a stack of printed circuit boards (PCBs) provides communication channels between a first coupling pad on the baseboard that has a first pattern of electrical contacts and a second coupling pad on top of the dual interposer substrate that provides the second pattern of electrical contacts. The second pattern receives another type of processor integrated circuit than a type supported by the first pattern. Stacked vias formed through the stack of PCBs electrically connect respective electrical contacts of the first and second coupling pads to form a corresponding communication channel. One or more grounded vias mitigate signal integrity (SI) anomalies on the communication channels.

A pluggable processor module includes a microprocessor package, a voltage regulator including a capacitor board, and contact pads that each include a first side in contact with the microprocessor package and a second side in contact with the capacitor board.

An apparatus, includes a PCB, a semiconductor package that includes a substrate and a stiffener with an opening, and at least one connection component. The stiffener is disposed on a top surface of the PCB. The at least one connection component is configured to connect the PCB to the semiconductor package. The at least one connection component may include another PCB that is disposed on the substrate within the opening of the stiffener and on the PCB. The at least one connection component may include an array of connectors that are disposed on the substrate within the opening of the stiffener, and may include a socket disposed on the PCB. The at least one connection component may include a BGA that is disposed on the substrate within the opening of the stiffener and on the PCB and on a pedestal portion of a surface of the PCB.

Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.

Systems and methods for the design and use of a System-in-Package (SiP) device with a connection layout for minimizing a system Printed Circuit Board (PCB) using the SiP are provided.

An information handling system (IHS) has a circuit board assembly with a dual-sided interposer substrate that is inserted between a baseboard and a processor integrated circuit having a second pattern of electrical contacts. The dual interposer substrate formed of a stack of printed circuit boards (PCBs) provides communication channels between a first coupling pad on the baseboard that has a first pattern of electrical contacts and a second coupling pad on top of the dual interposer substrate that provides the second pattern of electrical contacts. The second pattern receives another type of processor integrated circuit than a type supported by the first pattern. Stacked vias formed through the stack of PCBs electrically connect respective electrical contacts of the first and second coupling pads to form a corresponding communication channel. One or more grounded vias mitigate signal integrity (SI) anomalies on the communication channels.

An information handling system (IHS) has a circuit board assembly with a dual-sided interposer substrate that is inserted between a baseboard and a processor integrated circuit having a second pattern of electrical contacts. The dual interposer substrate formed of a stack of printed circuit boards (PCBs) provides communication channels between a first coupling pad on the baseboard that has a first pattern of electrical contacts and a second coupling pad on top of the dual interposer substrate that provides the second pattern of electrical contacts. The second pattern receives another type of processor integrated circuit than a type supported by the first pattern. Stacked vias formed through the stack of PCBs electrically connect respective electrical contacts of the first and second coupling pads to form a corresponding communication channel. One or more grounded vias mitigate signal integrity (SI) anomalies on the communication channels.

Various exemplary embodiments relate to a printed circuit board (PCB) for electrically connecting a discrete array component including a pattern formed on the PCB which is a merger of a set of via pads and a discrete array component; wherein the pattern is generated by a pin mapping between the discrete array component and a via grid array on the PCB; and wherein the pattern is formed of a metal etched during a manufacturing process of the PCB.