A surface-mounted integrated circuit (IC) package is disclosed that has unwanted flux removed from surface-mounted IC. A bottom termination component (BTC) includes lands and a thermal pad. The lands provide an electrical connection from the BTC and the thermal pad provides heat transfer from the BTC. The thermal pad includes vias that are configured to remove flux generated from solder applied to the surface-mounted IC as the surface-mounted IC is assembled. A printed circuit board (PCB) is mounted to the BTC and is electrically connected to the BTC via the lands and receives heat transfer from the BTC via the thermal pad and includes a reservoir. The reservoir is configured to pull flux positioned between the lands into the reservoir as the flux is generated from the solder applied to the surface-mounted IC as the BTC is mounted to the PCB and as the surface-mounted IC is assembled.

A semiconductor package and a method of forming the same are provided. The semiconductor package includes a package substrate, a semiconductor device, an underfill element, and a groove. The semiconductor device is bonded to the surface of the package substrate through multiple electrical connectors. The underfill element is formed between the semiconductor device and the surface of the package substrate to surround and protect the electrical connectors. The underfill element includes a fillet portion that extends laterally beyond the periphery of the semiconductor device and is formed along the periphery of the semiconductor device. The groove is formed in the fillet portion and spaced apart from the periphery of the semiconductor device.

A circuit board includes an insulating part including insulating layers, metal layers disposed on the insulating layers, vias each passing through at least one insulating layer among the insulating layers and connecting together at least two metal layers among the metal layers; a first thermally conductive structure including a thermally conductive material, at least a part of the thermally conductive structure being inserted into the insulating part, a first via having one surface contacting the first thermally conductive structure, a first metal pattern contacting another surface of the first via, a first bonding member connected to the first metal pattern, and pads to which a first electronic component is connected on an outermost surface of a metal layer disposed on an outermost surface of the insulating part, the pads being at least in a first region and a second region having a higher temperature than the first region.

A component carrier includes a first level stack of first plural of electrically conductive layer structures and/or first electrically insulating layer structures; a first component aligned within a first through hole cut out in the first level stack such that one of an upper or a lower surface of the first component is substantially flush with an respective upper or a lower surface of the first level stack second electrically conductive layer structures and/or second electrically insulating layer structures attached onto the upper and the lower surface of the first level stack thereby covering the first component at the upper and the lower surface of the first component and pressed to form a second level stack. A second component is aligned within a second through hole cut out in the second level stack such that one of upper or a lower surface of the second component is substantially flush with an upper or a lower surface of the second level stack.

A method for forming a semiconductor package is provided. The method includes mounting a semiconductor device on a surface of a package substrate. The method also includes forming an underfill element between the semiconductor device and the surface of the package substrate. The underfill element includes a fillet portion that extends laterally beyond the periphery of the semiconductor device and is formed along the periphery of the semiconductor device. The method also includes forming one or more grooves in the fillet portion.

A circuit board includes a substrate and multiple pads. The multiple pads are disposed on the substrate and have respective footprints for connecting one or more electronic components to the circuit board, at least a pad from among the pads includes a linear electrical trace laid out in a two-dimensional (2D) pattern that covers at least a part of a footprint of the pad.

Embodiments of the invention are directed to an integrated circuit (IC) package assembly, including: one or more printed circuit boards (PCBs); and a set of chip packages, each including: an overmold; and an IC chip, overmolded in the overmold, and wherein: the chip packages are stacked transversely to an average plane of each of the chip packages, thereby forming a stack wherein a main surface of one of the chip packages faces a main surface of another one of the chip packages; and each of the chip packages is laterally soldered to one or more of said one or more PCBs and arranged transversally to each of said one or more PCBs, whereby an average plane of each of said one or more PCBs extends transversely to the average plane of each of the chip packages of the stack. Further embodiments are directed to related devices and fabrication methods.

Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate with a first surface and a second surface opposite from the first surface. In an embodiment, pads are on the first surface of the package substrate, where the pads have a first width. In an embodiment, a layer is on the first surface of the package substrate, where the layer comprises wells through the layer, and where the wells have a second width that is wider than the first width. In an embodiment, a liquid metal is in the wells and in contact with the pads.

A land group with which a terminal group of a semiconductor package has been jointed, a conductor pattern which has been arranged in a mounting area where the semiconductor package was mounted and which has been jointed with a heat radiation plate of the semiconductor package, a conductor pattern at least a part of which has been arranged on the outside of the mounting area, and a conductor pattern which connects the conductor patterns are formed on a printed-wiring board. The land group includes a land adjacent to the conductor pattern and a land which is not adjacent to the conductor pattern. The land is formed in a shape different from that of the land so as to be away from the conductor pattern.

A film material includes a substrate and a film layer arranged on one main surface of the substrate. The film layer contains a fibrous first resin and a thermosetting second resin in an uncured or semi-cured state, and a linear expansion coefficient CF of the first resin is smaller than a linear expansion coefficient CR of the second resin in cured state.