A semiconductor structure and a method for manufacturing same. The semiconductor structure includes a storage unit, which includes: a first dielectric layer and a metal bit line located therein; a semiconductor channel, located on the metal bit line; a word line, disposed surrounding part of the semiconductor channel; a second dielectric layer, located between the metal bit line and the word line, and on top of the word line; a first and a second lower electrode layers, stacked on the semiconductor channel, the first lower electrode layer contacting the top surface of the semiconductor channel; an upper electrode layer, located on top of the second lower electrode layer, and surrounding the first and the second lower electrode layers; and a capacitor dielectric layer, located between the upper electrode layer and the first lower electrode layer, and between the upper electrode layer and the second lower electrode layer.

A semiconductor structure and a method for manufacturing the same, and a memory are provided. The semiconductor structure includes: a substrate, a plurality of oxide pillars, a plurality of active pillars, a first insulating layer and a storage structure. The plurality of oxide pillars are on the substrate and arranged in an array along a first direction and a second direction. Both the first direction and the second direction are parallel to a surface of the substrate, and the first direction intersects with the second direction. The first insulating layer is in a gap between the oxide pillars. Each active pillar is on a top surface of a corresponding one of the oxide pillars. The storage structure covers at least part of a side wall of the active pillar.

Embodiments provide a semiconductor structure and fabrication method. The method include: forming sacrificial layers on a sidewall of the first pattern mask layer and a sidewall of the second pattern mask layer, and forming a first filling layer filling a first spacing between the sacrificial layers; removing the first filling layer, the first pattern mask layer and the second pattern mask layer, retaining the sacrificial layers and the first spacing, and replacing a second spacing between the first pattern mask layer and the second pattern mask layer; forming a second filling layer filling the first spacing and the second spacing; etching the sacrificial layers based on the second filling layer to form etched patterns, and etching the pattern transfer layer and the target layer based on the etched patterns to form a first pattern target layer in the array region and a second pattern target layer in the peripheral region.

Embodiments of the disclosure provide a semiconductor structure and a method for forming the same. The method includes: providing a semiconductor substrate including a plurality of active pillars arranged at intervals; etching the active pillar to form an annular groove, in which the annular groove does not expose a top surface and a bottom surface of the active pillar; and forming a first semiconductor layer in the annular groove to form the semiconductor structure; in which a band gap of the first semiconductor layer is smaller than a band gap of the active pillar.

A semiconductor structure and a method for manufacturing a semiconductor structure are provided. The semiconductor structure includes: a substrate, first gate structures, second gate structures, and a covering layer. The substrate includes semiconductor channels spaced apart from each other and arranged at a top portion of the substrate and extending in a vertical direction. Each first gate structure is arranged in a first area of a respective semiconductor channel and is arranged around the respective semiconductor channel. Each second gate structure is arranged in a second area of a respective semiconductor channel and includes a ring structure and at least one bridge structure. The covering layer is arranged in a spaced area between any two adjacent semiconductor channels. The covering layer includes first interconnecting holes extending in the vertical direction.

A semiconductor structure includes a substrate, a gate structure, a cover layer and a first sacrificial structure. The substrate includes discrete semiconductor channels arranged at a top of the substrate. The gate structure is disposed in a middle region of a semiconductor channel, and includes a ring structure and a bridge structure. The ring structure encircles the semiconductor channel, and the bridge structure penetrates through the semiconductor channel and extends to an inner wall of the ring structure along a penetrating direction. The cover layer is located between adjacent semiconductor channels, and includes a first communication hole. The first sacrificial structure is located on the cover layer, and includes a second communication hole. An inner sidewall of the second communication hole has an irregular shape.

The present disclosure provides a method of manufacturing a semiconductor structure, and a semiconductor structure. The method of manufacturing a semiconductor structure includes: providing an initial structure, wherein the initial structure includes a substrate, a laminated structure, and capacitor units, and the laminated structure includes support layers; forming a first mask layer, wherein the first mask layer covers a top surface of the laminated structure; forming a first opening in the first mask layer, wherein the first opening exposes the top surface of the laminated structure, and a projection region of the first opening on the substrate at least partially overlaps with projection regions of the capacitor units on the substrate; forming a shielding structure, wherein the shielding structure is located in the first opening, and the shielding structure covers a sidewall of the first opening.

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a substrate, a gate structure and a dielectric layer. Herein, the substrate includes discrete semiconductor pillars. The semiconductor pillars are arranged at the top of the substrate and extend in a vertical direction. The substrate further includes a capacitor structure located at the top of the semiconductor pillar. The gate structure is arranged at the middle area of the semiconductor pillar and surrounds the semiconductor pillar. The dielectric layer is located between the gate structure and the semiconductor pillar, and covers the sidewall of the semiconductor pillar.

The present disclosure discloses a capacitor structure and its formation method and a memory. The method includes: providing a substrate; forming an electrode support structure on the substrate in a stacking fashion, wherein the electrode support structure includes at least a first support layer on its top, a capacitor hole is formed at intervals within the electrode support structure and extends upwards in a direction perpendicular to a surface of the substrate; forming, within the capacitor hole, an electrode post and an electrode layer extending from the electrode post to the upper surface of the first support layer; removing the electrode layer; removing the first support layer; forming a dielectric layer on the top of the electrode support structure, wherein the dielectric layer covers the top of the electrode post, and an outer peripheral wall of the top of the electrode post is connected with the dielectric layer.

Embodiments provide a method for fabricating an array structure of a columnar capacitor and a semiconductor structure, relating to the field of semiconductor manufacturing technology. In the method, before a mask layer is removed, a thickness of the mask layer in the peripheral region is first adjusted to be equal to a thickness of the mask layer in the array region, thereby avoiding damage to a top support layer caused by different thicknesses of the mask layer. Moreover, in the method, a thickness of the top support layer is increased by means of a supplementary support layer, to increase support strength of the top support layer, thereby further preventing occurrence of tilt of the columnar capacitor due to insufficient support strength of the top support layer.