The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate, where the substrate includes a complete die region and an incomplete die region; forming a stack on the substrate, where the stack includes sacrificial layers and supporting layers; forming a first photoresist layer on the stack; exposing the first photoresist layer, and developing to remove the first photoresist layer on the incomplete die region; and etching the stack by using the first photoresist layer on the complete die region as a mask.

A memory device and a forming method thereof are provided. The memory device includes: a semiconductor substrate, wherein multiple active regions are formed in the semiconductor substrate, and the multiple active regions are separated by multiple first trenches extending along a first direction and multiple second trenches extending along a second direction; a third trench, extending along the first direction and located in the semiconductor substrate at the bottom of the first trench; a bit line doped region, located in the semiconductor substrate on two sides of the third trench; a gate dielectric layer, located on a sidewall surface of the first trench and a sidewall surface of the second trench; a first dielectric layer that fills the third trench; a metal gate, located in the second trench and the first trench on the first dielectric layer.

A method of manufacturing a semiconductor device includes forming a preliminary lower electrode layer on a substrate, the preliminary lower electrode layer including a niobium oxide; converting at least a portion of the preliminary lower electrode layer to a first lower electrode layer comprising a niobium nitride by performing a nitridation process on the preliminary lower electrode layer; forming a dielectric layer on the first lower electrode layer; and forming an upper electrode on the dielectric layer.

The present disclosure provides a method for preparing a semiconductor memory device with air gaps between conductive features. The method includes forming an isolation layer defining a first active region in a substrate; forming a first doped region in the first active region; forming a first word line buried in a first trench adjacent to the first doped region; and forming a high-level bit line contact positioned on the first doped region; forming a first air gap surrounding the high-level bit line contact. The forming of the first word line comprises: forming a lower electrode structure and an upper electrode structure on the lower electrode structure. The forming of the upper electrode structure comprises: forming a source layer substantially covering a sidewall of the first trench; forming a conductive layer on the source layer; and forming a work-function adjustment layer disposed between the source layer and the conductive layer.

A semiconductor device includes an insulating base including a trench, a transistor including a gate electrode and vertical channel in the trench, and a source electrode in the insulating base outside the trench, an isolation layer on the gate electrode in the trench, and a capacitor including a trench capacitor portion that is on the isolation layer in the trench, and a stacked capacitor portion that is coupled to the source electrode of the transistor outside the trench.

A method for manufacturing a stacked capacitor structure includes: forming a first patterned structure over a substrate; forming a first bottom electrode over the first patterned structure; depositing a first dielectric film over the first bottom electrode; depositing a first top electrode layer over the first dielectric film; forming a first vertical interconnect structure; forming a second patterned structure over the first top electrode layer; forming a second bottom electrode over the second patterned structure and electrically connected to the first bottom electrode through the first vertical interconnect structure; depositing a second dielectric film over the second bottom electrode; depositing a second top electrode layer over the second dielectric film; and forming a second vertical interconnect structure extending from the first top electrode layer. The second top electrode layer is electrically connected to the first top electrode layer through the second vertical interconnect structure.

A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

A device is disclosed. The device includes a plurality of capacitors, a transistor connected to each of the plurality of capacitors, and a first dielectric layer and a second dielectric layer on respective adjacent sides of adjacent capacitors of the plurality of capacitors. The first dielectric layer and the second dielectric layer include a top portion and a bottom portion, the top portion of the first dielectric layer and the top portion of the second dielectric layer extend from respective directions and meet at a top portion of a space between the adjacent capacitors, the bottom portion of the first dielectric layer and the bottom portion of the second dielectric layer extend from respective directions and meet at a bottom portion of a space between the adjacent capacitors. The device also includes one or more air-gaps surrounded by the first dielectric layer and the second dielectric layer on respective adjacent sides of the adjacent capacitors, the top portion of the first dielectric layer and the second dielectric layer between the adjacent capacitors, and the bottom portion of the first dielectric layer and the second dielectric layer between the adjacent capacitors.

A semiconductor device comprises, a substrate, a first capacitor structure including a plurality of first storage electrodes on the substrate, a first upper electrode on the first storage electrodes and a first capacitor dielectric layer between the plurality of first storage electrodes and the first upper electrode, and a first lower electrode between the first capacitor structure and the substrate and electrically connected with the first capacitor structure. The plurality of first storage electrodes include a first normal storage electrode and a first dummy storage electrode, which are spaced apart from each other. The first normal storage electrode is electrically connected with the first lower electrode, and the first dummy storage electrode is not electrically connected with the first lower electrode.

A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate and a conductive pad disposed on the substrate and having a first surface facing away from the substrate. The first surface of the conductive pad is recessed toward the substrate and defines a recessed portion. The semiconductor device also includes a capacitor structure at least partially-disposed within the recessed portion of the conductive pad and electrically connected with the substrate through the conductive pad.