A semiconductor structure includes a substrate, a drain region, a word line, a gate structure, and a first bit line. The drain region is disposed on the substrate. The gate structure is disposed on the drain region and has a portion in the word line. The first bit line is disposed on the gate structure to serve as a source region.

Methods, apparatuses, and systems related to forming a capacitor using a hard mask material are described. An example method includes patterning a surface to have a first silicate material, a first nitride material on the first silicate material, a second silicate material on the first nitride material, a second nitride material on the second silicate material, and a sacrificial material on the second nitride material. The method further includes forming a hard mask material on the sacrificial material. The method further includes forming a capacitor material in an opening through the first silicate material, the first nitride material, the second silicate material, the second nitride material, the sacrificial material, and the hard mask material. The method further includes removing the sacrificial material and the hard mask material.

Methods, apparatuses, and systems related to forming a recess in a semiconductor structure are described. An example method includes etching the semiconductor structure using an elevated temperature dilution of acid and water. The method further includes etching the semiconductor structure using a room temperature wet etch of acid and water and a surface modification chemistry.

A method of manufacturing a semiconductor device, which has buried gate electrodes, includes: forming a plurality of gate trenches in a substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches crossing the plurality of active regions and extending parallel to each other in a first horizontal direction; selectively forming a first gate insulating layer on an exposed surface of the substrate; forming a second gate insulating layer on exposed surfaces of both the first gate insulating layer and the device isolation film; and forming a plurality of gate insulating layers by partially removing the first gate insulating layer and the second gate insulating layer, and forming a plurality of buried gate electrodes.

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) within the substrate, and an interconnect structure over the DTC and the substrate. The interconnect structure includes a seal ring structure in electrical contact with the substrate, a first conductive via in electrical contact with the DTC, and a first conductive line electrically coupling the seal ring structure to the first conductive via.

A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.

According to an embodiment, a capacitor includes a conductive substrate, a conductive layer, and a dielectric layer. The conductive substrate has a first main surface and a second main surface and is provided with a plurality of recesses on the first main surface. The conductive substrate is further provided with a plurality of holes in one or more portions each sandwiched between two adjacent ones of the recesses such that a region on a side of the first main surface has a larger porosity than a region on a side of the second main surface. The conductive layer covers the first main surface, side walls and bottom surfaces of the recesses, and walls of the holes. The dielectric layer is interposed between the conductive substrate and the conductive layer.

A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.

A semiconductor memory device includes a transistor having a gate, a source and a drain and a metal-insulator-semiconductor (MIS) structure. The transistor and the MIS structure are disposed on a common substrate. The MIS structure includes a dielectric layer disposed on a semiconductor region, and an electrode electrically disposed on the dielectric layer and coupled to the drain of the transistor. The electrode includes a bulk portion and a high-resistance portion, both disposed on the dielectric layer. The high-resistance portion has a resistance value in a range from 1.010.sup.4 cm to 1.010.sup.4 cm or a sheet resistance in a range from 1.010.sup.2/ to 1.010.sup.10/.

An apparatus comprises first electrodes vertically extending through an isolation material, a second electrode horizontally intervening between two or more of the first electrodes laterally neighboring one another, and a dielectric structure horizontally and vertically intervening between the second electrode and the two or more of the first electrodes. Additional apparatuses, memory devices, electronic systems, and a method of forming an apparatus are also described.