Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.

Embodiments provide a semiconductor structure and a fabricating method. The semiconductor structure includes: a substrate, where a trench is formed in the substrate; a conductive layer positioned in the trench, where the conductive layer includes a first conductive layer and a second conductive layer, the second conductive layer is positioned on the first conductive layer, and a projection area of a bottom of the second conductive layer within the trench is greater than a projection area of a top of the first conductive layer within the trench; a dielectric layer positioned between the conductive layer and an inner wall of the trench, where a top of the dielectric layer is lower than the top of the first conductive layer; an isolation layer positioned on the conductive layer; and a void defined by the isolation layer, the conductive layer, the dielectric layer, and a side wall of the trench.

Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

The present application discloses a method for fabricating the semiconductor device. The method for fabricating a semiconductor device includes providing a substrate having a first lattice constant and forming a first word line positioned in the substrate and a plurality of stress regions positioned adjacent to lower portions of sidewalls of the first word line. The plurality of stress regions have a second lattice constant, the second lattice constant of the plurality of stress regions is different from the first lattice constant of the substrate.

Disclosed are DRAM devices and methods of forming DRAM devices. One non-limiting method may include providing a device, the device including a plurality of angled structures formed from a substrate, a bitline and a dielectric between each of the plurality of angled structures, and a drain disposed along each of the plurality of angled structures. The method may further include providing a plurality of mask structures of a patterned masking layer over the plurality of angled structures, the plurality of mask structures being oriented perpendicular to the plurality of angled structures. The method may further include etching the device at a non-zero angle to form a plurality of pillar structures.

The present application provides a method for fabricating a semiconductor device including providing a substrate, concurrently forming a first conductive line and a bottom contact on the substrate, concurrently forming a first conductive line spacer on a sidewall of the first conductive line and a bottom contact spacer on a sidewall of the bottom contact, forming a first insulating layer over the substrate and concurrently forming an air gap between the first conductive line spacer and the bottom contact spacer.

Provided is a dynamic random access memory including a substrate, a gate dielectric layer, a metal filling layer, an adhesion layer, multiple work function layers, and multiple doped regions. The substrate has a trench. The gate dielectric layer is located on a sidewall and a bottom surface of the trench. The metal filling layer is located in the trench. The adhesion layer is located between the gate dielectric layer and the metal filling layer. The work function layers are located in the trench, where each work function layer is located between a sidewall of the gate dielectric layer and a sidewall of the adhesion layer. The doped regions are located in the substrate on both sides of the trench, where part of the work function layers and part of the gate dielectric layer are laterally sandwiched between part of the doped regions and part of the adhesion layer.

A semiconductor device manufacturing method according to the exemplary embodiments of the disclosure includes patterning a substrate, thereby forming an active pattern, forming a trench penetrating the active pattern, forming a support layer covering the trench, forming a first opening at the support layer, forming a gate electrode layer filling the trench through the first opening, and forming a bit line structure electrically connected to the active pattern. The support layer includes a base portion covering a top surface of the active pattern, and a support disposed in the trench.

A semiconductor structure includes a semiconductor substrate including a first active region and a chop region. The semiconductor structure also includes a source/drain region disposed in the first active region, an isolation structure disposed in the chop region, and a gate structure extending at least across the isolation structure in the chop region. The gate structure includes a gate electrode layer and a gate lining layer lining on the gate electrode layer. The gate lining layer includes a first portion having an upper surface that is lower than a bottom surface of the source/drain region.

A semiconductor memory device may be formed by a method of fabricating the same. The method may include forming a buffer insulating layer on a semiconductor substrate including active portions, forming bit line structures on the buffer insulating layer, forming bit line spacers on side surfaces of each of the bit line structures, patterning the buffer insulating layer to form gap regions extending in a first direction, the gap regions formed between the bit line structures and exposing portions of the active portions, forming a protection oxide layer to cover the portions of the active portions exposed through the gap regions, forming a mold layer to fill the gap regions, in which the protection oxide layer is formed, forming mold patterns respectively in each of the gap regions to be spaced apart from each other, forming fence patterns in each of the gap regions and between the mold patterns, removing the mold patterns to form contact regions exposing the protection oxide layer, removing the protection oxide layer, and forming buried contact patterns in the contact regions to contact the portions of the active portions.