Embodiments provide a semiconductor structure and a fabrication method. The method includes: providing a substrate, the substrate being provided with a plurality of first trenches extending along a first direction and a plurality of second trenches extending along a second direction, and a depth of each of the plurality of first trenches being less than a depth of each of the plurality of second trenches; forming a first isolation structure to cover the substrate and fill the plurality of first trenches and the plurality of second trenches; forming a plurality of third trenches positioned in the substrate at bottoms of the plurality of first trenches and extending along the first direction; forming a second isolation structure to fill the plurality of first trenches and the plurality of third trenches; forming gate structures surrounding the substrate between the plurality of first trenches along the second direction.

Embodiments of the present application provide a method of fabricating a memory, the method comprises: providing a substrate, wherein grooves are disposed in the substrate; forming a gate insulation layer on a surface of each groove; forming a metal layer on the gate insulation layer, the metal layer being at least fully filled in the groove; surface-processing the metal layer, to enhance flatness of a surface of the metal layer; and etching to remove the metal layer by a certain thickness to form a gate electrode whose top is lower than a surface of the substrate. Embodiments of the present application facilitate to solve the problem of unevenness at the top surface of the gate electrode.

The present disclosure relates to the field of semiconductor technologies, and provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a semiconductor base, bit lines and word lines, wherein a plurality of active regions is provided in the semiconductor base; the bit lines are disposed in the semiconductor base, extend in a first direction and are connected to the active regions; and the word lines are disposed on the semiconductor base above the bit lines, extend in a second direction, and intersect with the active regions.

The present invention relates to a semiconductor device with improved reliability and a method for manufacturing the same. A semiconductor device according to the present invention may comprise: a substrate including a gate trench; a gate insulating layer formed on a surface of the gate trench; and silicon-doped metal nitride on the gate insulating layer, wherein the silicon-doped metal nitride has a silicon concentration of less than 1 at %.

The present application discloses a method for fabricating a semiconductor device including providing a substrate comprising an array region and a peripheral region surrounding the array region, forming a first semiconductor element positioned above the peripheral region and having a first threshold voltage and a second semiconductor element positioned above the peripheral region and having a second threshold voltage, and forming a plurality of capacitor structures positioned above the peripheral region of the substrate. The first threshold voltage of the first semiconductor element is different from the second threshold voltage of the second semiconductor element.

A transistor structure includes a gate conductive region, a gate dielectric region, a channel region and a drain region. The gate conductive region is below an original surface of a substrate. The gate dielectric region surrounds the gate conductive region. The channel region surrounds the gate dielectric region. The drain region is horizontally spaced apart from the gate conductive region, wherein the drain region includes a highly doped region; wherein the gate dielectric region includes a first dielectric portion and a second dielectric portion, the first dielectric portion is positioned between the gate conductive region and the highly doped region, and the second dielectric portion is positioned between the gate conductive region and the channel region; wherein a horizontal thickness of the first dielectric portion is greater than that of the second dielectric portion.

A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first bit line structure positioned above the substrate and including a first line portion arranged in parallel to a first direction, and a second line portion connecting to a first end of the first line portion and arranged in parallel to a second direction in perpendicular to the first direction; a first bit line top contact including a first bar portion positioned on the first end of the first line portion and arranged in parallel to the first direction, and a second bar portion connecting to a first end of the first bar portion, positioned on the second line portion, and arranged in parallel to the second direction; and a first top conductive layer electrically coupled to the first bit line top contact.

An integrated circuit device includes a substrate including an active region defined by a device isolation layer, the substrate defining a gate trench extending across the active region, a gate dielectric layer conformally covering an inner surface of the gate trench, and a gate electrode filling the gate trench on the gate dielectric layer. The gate electrode is composed of crystal grains of a single metal, and a diagonal length of at least one of the crystal grains is greater than a height of the active region that is in contact with the gate electrode.

A semiconductor structure and a method of manufacturing a semiconductor structure are provided. The method includes forming a conductive layer on a precursor memory structure, in which the precursor memory structure includes a plurality of transistors and a plurality of contact plugs disposed on and connected to the transistors. The conductive layer in a TEG region is then patterned to form a first patterned conductive layer on the precursor memory structure. The first patterned conductive layer is then patterned to form a plurality of first landing pads extending along a first direction, in which the first landing pads are separated from each other in a second direction that is different from the first direction and are electrically connected to each other through the contact plugs and the transistors.